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db14-000165-01 LSI53C875/875e pci to ultra scsi i/o processor technical manual april 2003 version 4.2
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?er is prohibited. document db14-000165-01, sixth edition (april 2003) this document describes the lsi logic LSI53C875/875e pci to ultra scsi i/o processor and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 1998?001/2003 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, sdms, and scripts are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
preface iii preface this book is the primary reference and technical manual for the lsi logic LSI53C875/875e pci to ultra scsi i/o processor. it contains a complete functional description for the LSI53C875/875e and includes complete physical and electrical speci?ations for the LSI53C875/875e. audience this technical manual is intended for system designers and programmers who are using this device to design a scsi port for pci-based personal computers, workstations, or embedded applications. organization this document has the following chapters and appendixes: ? chapter 1, general description , includes general information about the LSI53C875 and other members of the lsi53c8xx family of pci to scsi i/o processors. ? chapter 2, functional description , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus. ? chapter 3, pci functional description , describes the chips connection to the pci bus, including the pci commands and con?uration registers supported. ? chapter 4, signal descriptions , contains the pin diagrams and de?itions of each signal. ? chapter 5, scsi operating registers , describes each bit in the operating registers, organized by address.
iv preface ? chapter 6, instruction set of the i/o processor , de?es all of the scsi scripts instructions that are supported by the LSI53C875. ? chapter 7, instruction set of the i/o processor , contains the electrical characteristics and ac timings for the chip. ? appendix a, register summary , is a register summary. ? appendix b, external memory interface diagram examples , contains several example interface drawings to connect the LSI53C875 to an external rom. related publications for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2); x3.253 ( scsi-3 parallel interface ) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface
preface v lsi logic world wide web home page www.lsilogic.com scsi scripts processors programming guide , version 2.2, order number s14044.a pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111. revision record revision date remarks 1.0 6/95 revision 1.0 2.0 3/96 revision 2.0. fast-20 changed to ultra scsi throughout. 3.0 9/96 revision 3.0. minor copy changes throughout. 4.0 2/98 revision 4.0. minor copy changes throughout 4.1 3/01 product names changed from sym to lsi. 4.2 4/03 revision 4.2. correct v dd -s in table 4.3
vi preface
contents vii contents chapter 1 general description 1.1 package and feature options 1-4 1.2 bene?s of ultra scsi 1-4 1.3 tolerant technology 1-5 1.4 LSI53C875 bene?s summary 1-6 1.4.1 scsi performance 1-6 1.4.2 pci performance 1-7 1.4.3 integration 1-7 1.4.4 ease of use 1-7 1.4.5 flexibility 1-8 1.4.6 reliability 1-9 1.4.7 testability 1-9 chapter 2 functional description 2.1 scsi functional description 2-1 2.1.1 scsi core 2-1 2.1.2 dma core 2-2 2.1.3 scripts processor 2-2 2.1.4 internal scripts ram 2-3 2.1.5 sdms software: the total scsi solution 2-3 2.2 designing an ultra scsi system 2-4 2.2.1 using the scsi clock doubler 2-4 2.3 prefetching scripts instructions 2-5 2.3.1 opcode fetch burst capability 2-6 2.4 external memory interface 2-6 2.5 pci cache mode 2-8 2.5.1 load/store instructions 2-8 2.5.2 3.3 v/5 v pci interface 2-9 2.5.3 additional access to general purpose pins 2-9
viii contents 2.5.4 jtag boundary scan testing 2-10 2.5.5 big and little endian support 2-10 2.5.6 loopback mode 2-12 2.5.7 parity options 2-12 2.5.8 dma fifo 2-15 2.5.9 scsi bus interface 2-19 2.5.10 select/reselect during selection/reselection 2-25 2.5.11 synchronous operation 2-25 2.5.12 ultra scsi synchronous data transfers 2-27 2.5.13 interrupt handling 2-28 2.5.14 chained block moves 2-34 2.6 power management 2-38 2.6.1 power state d0 2-38 2.6.2 power state d3 2-39 chapter 3 pci functional description 3.1 pci addressing 3-1 3.1.1 pci bus commands and functions supported 3-2 3.2 pci cache mode 3-4 3.2.1 support for pci cache line size register 3-4 3.2.2 selection of cache line size 3-5 3.2.3 alignment 3-5 3.2.4 memory move misalignment 3-6 3.2.5 memory write and invalidate command 3-6 3.2.6 memory read line command 3-8 3.2.7 memory read multiple command 3-9 3.3 con?uration registers 3-11 chapter 4 signal descriptions 4.1 mad bus programming 4-22 chapter 5 scsi operating registers chapter 6 instruction set of the i/o processor 6.1 scsi scripts 6-1 6.1.1 sample operation 6-3
contents ix 6.2 block move instructions 6-5 6.2.1 first dword 6-5 6.2.2 second dword 6-12 6.3 i/o instruction 6-12 6.3.1 first dword 6-12 6.3.2 second dword 6-21 6.4 read/write instructions 6-21 6.4.1 first dword 6-21 6.4.2 second dword 6-22 6.4.3 read-modify-write cycles 6-22 6.4.4 move to/from sfbr cycles 6-24 6.5 transfer control instructions 6-26 6.5.1 first dword 6-26 6.5.2 second dword 6-33 6.6 memory move instructions 6-33 6.6.1 read/write system memory from scripts 6-34 6.6.2 second dword 6-35 6.6.3 third dword 6-35 6.7 load and store instructions 6-37 6.7.1 first dword 6-38 6.7.2 second dword 6-39 chapter 7 instruction set of the i/o processor 7.1 dc characteristics 7-1 7.2 tolerant technology electrical characteristics 7-7 7.3 ac characteristics 7-10 7.4 pci and external memory interface timing diagrams 7-13 7.4.1 target timing 7-15 7.4.2 initiator timing 7-24 7.4.3 external memory timing 7-32 7.5 pci and external memory interface timing 7-50 7.6 scsi timing diagrams 7-51 7.7 package drawings 7-58 appendix a register summary appendix b external memory interface diagram examples
x contents index customer feedback figures 1.1 LSI53C875 external memory interface 1-2 1.2 LSI53C875 chip block diagram 1-3 2.1 dma fifo sections 2-15 2.2 LSI53C875 host interface data paths 2-16 2.3 differential wiring diagram 2-22 2.4 regulated termination 2-24 2.5 determining the synchronous transfer rate 2-26 2.6 block move and chained block move instructions 2-35 4.1 LSI53C875 pin diagram 4-2 4.2 LSI53C875j pin diagram 4-3 4.3 LSI53C875n pin diagram 4-4 4.4 LSI53C875jb pin diagram (top view) 4-5 4.5 LSI53C875 functional signal grouping 4-9 6.1 scripts overview 6-4 6.2 block move instruction register 6-7 6.3 i/o instruction register 6-15 6.4 read/write instruction register 6-23 6.5 transfer control instructions 6-28 6.6 memory move instruction 6-36 6.7 load and store instruction format 6-40 7.1 rise and fall time test conditions 7-8 7.2 scsi input filtering 7-8 7.3 hysteresis of scsi receiver 7-9 7.4 input current as a function of input voltage 7-9 7.5 output current as function of output voltage 7-10 7.6 clock waveforms 7-11 7.7 reset input 7-12 7.8 interrupt output 7-13 7.9 pci con?uration register read 7-15 7.10 pci con?uration register write 7-16 7.11 operating register/scripts ram read 7-17
contents xi 7.12 operating register/scripts ram write 7-18 7.13 external memory read 7-20 7.14 external memory write 7-22 7.15 opcode fetch, nonburst 7-24 7.16 burst opcode fetch 7-25 7.17 back-to-back read 7-26 7.18 back-to-back write 7-27 7.19 burst read 7-28 7.20 burst write 7-30 7.21 read cycle, normal/fast memory ( 64 kbytes), single byte access 7-32 7.22 write cycle, normal/fast memory ( 64 kbytes), single byte access 7-34 7.23 read cycle, normal/fast memory ( 64 kbyte), multiple byte access 7-36 7.24 write cycle, normal/fast memory ( 64 kbyte), multiple byte access 7-38 7.25 read cycle, slow memory ( 64 kbyte) 7-40 7.26 write cycle, slow memory ( 64 kbyte) 7-42 7.27 read cycle, normal/fast memory ( 64 kbyte) 7-44 7.28 write cycle, normal/fast memory ( 64 kbyte) 7-45 7.29 read cycle, slow memory ( 64 kbyte) 7-46 7.30 write cycle, slow memory ( 64 kbyte) 7-48 7.31 initiator asynchronous send 7-51 7.32 initiator asynchronous receive 7-52 7.33 target asynchronous send 7-52 7.34 target asynchronous receive 7-53 7.35 initiator and target synchronous transfer 7-53 7.36 169-pin pbga (gv) mechanical drawing 7-58 7.37 160-pin pqfp (p3) mechanical drawing 7-59 b.1 64 kbyte interface with 200 ns memory b-1 b.2 64 kbyte interface with 150 ns memory b-2 b.3 256 kbyte interface with 150 ns memory b-3 b.4 512 kbyte interface with 150 ns memory b-4
xii contents tables 2.1 external memory support 2-7 2.2 bits used for parity control and generation 2-13 2.3 scsi parity control 2-14 2.4 scsi parity errors and interrupts 2-15 2.5 differential mode 2-20 3.1 pci bus commands and encoding types 3-3 3.2 pci con?uration register map 3-12 4.1 LSI53C875, LSI53C875j, LSI53C875e, and LSI53C875je power and ground signals 4-7 4.2 LSI53C875n power and ground signals 4-7 4.3 LSI53C875jb and LSI53C875jbe power and ground signals 4-8 4.4 system signals 4-10 4.5 address and data signals 4-11 4.6 interface control signals 4-12 4.7 arbitration signals 4-13 4.8 error reporting signals 4-14 4.9 scsi signals 4-15 4.10 additional interface signals 4-18 4.11 external memory interface signals 4-21 4.12 jtag signals (LSI53C875j/LSI53C875n/LSI53C875jb only) 4-22 4.13 subsystem data con?uration table for the LSI53C875e (pci rev id 0x26) 4-23 4.14 subsystem data con?uration table for the LSI53C875 (pci rev id 0x04), revision g only 4-23 4.15 external memory support 4-24 5.1 LSI53C875 register map 5-2 5.2 examples of synchronous transfer periods for scsi-1 transfer rates 5-16 5.3 example transfer periods for fast scsi-2 and ultra scsi transfer rates 5-17 5.4 maximum synchronous offset 5-18 5.5 scsi synchronous data fifo word count 5-28 6.1 scripts instructions 6-2 6.2 read/write instructions 6-24
contents xiii 7.1 absolute maximum stress ratings 7-2 7.2 operating conditions 7-2 7.3 scsi signals?d[15:0]/, sdp[1:0]/, sreq/, sack/ 7-3 7.4 scsi signals?msg, si_o/, sc_d/, satn/, sbsy/, ssel/, srst/ 7-3 7.5 input signals?lk, sclk, gnt/, idsel, rst/, testin, diffsens, big_lit/ 7-3 7.6 capacitance 7-4 7.7 output signals?ac/_testout, req/ 7-4 7.8 output signals?rq/, sdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/, mwe/ 7-4 7.9 output signal?err/ 7-4 7.10 bidirectional signals?d[31:0], c_be[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par 7-5 7.11 bidirectional signals?pio0_fetch/, gpio1_master/, gpio2_mas2/, gpio3, gpio4 7-5 7.12 bidirectional signals?ad[7:0] 7-6 7.13 input signals?di, tms, tck (LSI53C875j, LSI53C875jb, LSI53C875n only) 7-6 7.14 output signal?do (LSI53C875, LSI53C875jb, LSI53C875n only) 7-6 7.15 tolerant technology electrical characteristics 7-7 7.16 clock timing 7-11 7.17 reset input 7-12 7.18 interrupt output 7-13 7.19 LSI53C875 pci and external memory interface timing 7-50 7.20 initiator asynchronous send 7-51 7.21 initiator asynchronous receive 7-52 7.22 target asynchronous send 7-52 7.23 target asynchronous receive 7-53 7.24 scsi-1 transfers (se, 5.0 mbytes/s) 7-54 7.25 scsi-1 transfers (differential, 4.17 mbytes/s) 7-54 7.26 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock 7-55 7.27 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 50 mhz clock 7-55 7.28 ultra scsi se transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock 7-56
xiv contents 7.29 ultra scsi differential transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock 7-57 a.1 con?uration registers a-1 a.2 LSI53C875 register map a-2
LSI53C875/875e pci to ultra scsi i/o processor 1-1 chapter 1 general description chapter 1 is divided into the following sections: ? section 1.1, ?ackage and feature options ? section 1.2, ?ene?s of ultra scsi ? section 1.3, ?olerant technology ? section 1.4, ?si53c875 bene?s summary this manual combines information on the LSI53C875 and LSI53C875e, which are pci to ultra scsi i/o processors. the LSI53C875e is a minor modi?ation of the existing LSI53C875 product. it has all the functionality of the LSI53C875 with the addition of features to enable it to comply with the microsoft pc 97 hardware design guide. speci?ally, the LSI53C875e has a power management support enhancement. because there are only slight differences between them, the LSI53C875 and LSI53C875e are referred to as LSI53C875 throughout this technical manual. only the new enhancements are referred to as LSI53C875e. this technical manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided in the preface of this document. the LSI53C875 brings high-performance i/o solutions to host adapter, workstation, and general computer designs, making it easy to add scsi to any pci system. the LSI53C875 has a local memory bus for local storage of the devices bios rom in flash memory or standard eproms. most versions of the LSI53C875 support big and little endian byte addressing to accommodate a variety of data con?urations. the LSI53C875 supports programming of local flash memory for updates to bios or scripts programs.
1-2 general description the LSI53C875 is a pin-for-pin replacement for the lsi53c825 pci to scsi i/o processor, with added support for the scsi-3 ultra standard as well as other new features. some software enhancements are needed to take advantage of the features and ultra scsi transfer rates supported by the LSI53C875. the LSI53C875 performs ultra scsi transfers or fast 8- or 16- bit scsi transfers in single-ended (se) or differential mode, and improves performance by optimizing pci bus utilization. a system diagram showing the connections of the LSI53C875 with an external rom or flash memory is pictured in figure 1.1 . figure 1.1 LSI53C875 external memory interface pci bus scsi bus big_lit LSI53C875 gpio2_mas2/ mas1/ mwe/ moe/ mce/ mad[7:0] mas0/ gpio4 v pp translator v pp (optional) v pp hct374 hct374 hct374 rom or flash d[7:0] a[7:0] a[15:8] a[19:16] (optional) memory
1-3 a block diagram of the LSI53C875 is pictured in figure 1.2 . figure 1.2 LSI53C875 chip block diagram the LSI53C875 integrates a high-performance scsi core, a pci bus master dma core, and the lsi logic scsi scripts processor to meet the ?xibility requirements of scsi-3 and ultra scsi standards. it is designed to implement multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. the LSI53C875 is fully supported by the lsi logic storage device management system (sdms), a software package that supports the advanced scsi protocol interface (aspi) and the ansi common access method (cam). sdms software provides bios and driver support for hard disk, tape, removable media products, and cd-rom under the major pc operating systems. pci master and slave control block data fifo 536 bytes memory control scsi scripts processor operating registers con?uration registers scripts ram scsi fifo and scsi control block local bus memory tolerant drivers and receivers scsi bus external memory pci
1-4 general description 1.1 package and feature options the LSI53C875 is available in three versions with different packaging and feature options. the LSI53C875 is packaged in a 160-pin plastic quad flat pack (pqfp). the LSI53C875j is identical to the LSI53C875 with additional pins that support jtag boundary scan testing. the jtag boundary scan signals replace the testin, mac/_testout, big_lit/, and sdirp1 pins. the LSI53C875n includes all of the signals in the LSI53C875, with the addition of the jtag pins and four additional signals for extended parity checking and generation. it is packaged in a 208-pin pqfp. the LSI53C875jb is identical to the LSI53C875j, but is packaged in a 169-pin ball grid array (bga). the LSI53C875e, LSI53C875je, and LSI53C875jbe have been upgraded to include the power management features. 1.2 bene?s of ultra scsi ultra scsi is an extension of the scsi-3 standard that expands the bandwidth of the scsi bus and allows faster synchronous scsi transfer rates. when enabled, ultra scsi performs 20 megatransfers during an i/o operation, resulting in approximately twice the synchronous transfer rates of fast scsi-2. the LSI53C875 can perform 8-bit, ultra scsi synchronous transfers as fast as 20 mbytes/s. this advantage is most noticeable in heavily loaded systems, or large block size requirements, such as video on-demand and image processing. an advantage of ultra scsi is that it signi?antly improves scsi bandwidth while preserving existing hardware and software investments. the LSI53C875 is compatible with all existing lsi53c825 and lsi53c825a software; the only changes required are to enable the chip to perform synchronous negotiations for ultra scsi rates. the LSI53C875 can use the same board socket as an lsi53c825, with the addition of an 80 mhz sclk or enabling the internal scsi clock doubler to provide the correct frequency when transferring synchronous scsi data at 50 nanosecond transfer rates. some changes to existing cabling or system designs may be needed to maintain signal integrity at ultra scsi synchronous transfer rates. these design issues are discussed in chapter 2, ?unctional description.
tolerant technology 1-5 1.3 tolerant technology the LSI53C875 features tolerant technology, which includes active negation on the scsi drivers and input signal ?tering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. active negation is enabled by setting bit 7 in the scsi test three (stest3) register. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant receivers ?ter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input ?ters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. tolerant technology input signal ?tering is a built-in feature of the LSI53C875 and all lsi logic fast scsi devices. on the LSI53C875, the user may select a ?tering period of 30 or 60 ns, with bit 1 in the scsi test two (stest2) register. the bene?s of tolerant technology include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute.
1-6 general description 1.4 LSI53C875 bene?s summary the section provides an overview of the LSI53C875 features and bene?s. it contains information on scsi performance , pci performance , integration , ease of use , flexibility , reliability , and testability . 1.4.1 scsi performance to improve scsi performance, the LSI53C875: ? includes 4 kbyte internal ram for scripts instruction storage. ? performs wide, ultra scsi synchronous transfers as fast as 40 mbytes/s. ? increases scsi synchronous offset from 8 to 16 levels. ? supports variable block size and scatter/gather data transfers. ? performs sustained memory-to-memory dma transfers faster than 47 mbytes/s (@ 33 mhz). ? minimizes scsi i/o start latency. ? performs complex bus sequences without interrupts, including restore data pointers. ? reduces interrupt service routine overhead through a unique interrupt status reporting method. ? performs fast and wide scsi bus transfers in se and differential mode. 10 mbytes/s asynchronous (20 mbytes/s with ultra scsi). 20 mbytes/s synchronous (40 mbytes/s with ultra scsi). ? supports load and store scripts instructions to increase the performance of data transfers to and from chip registers. ? supports target disconnect and later reconnect with no interrupt to the system processor. ? supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching. ? supports expanded register move instructions to support additional arithmetic capability. ? complies with pci bus power management speci?ation (LSI53C875e) revision 1.0.
LSI53C875 bene?s summary 1-7 1.4.2 pci performance to improve pci performance, the LSI53C875: ? complies with pci 2.1 speci?ation. ? bursts 2, 4, 8, 16, 32, 64, or 128 dwords across pci bus. ? supports 32-bit word data bursts with variable burst lengths. ? prefetches up to 8 dwords of scripts instructions. ? bursts scripts opcode fetches across the pci bus. ? performs zero wait-state bus master data bursts faster than 110 mbytes/s (@ 33 mhz). ? supports pci cache line size register. ? supports pci write and invalidate, read line, and read multiple commands. 1.4.3 integration the following features ease integration of the LSI53C875 into a system: ? 3.3 v/5 v pci interface. ? full 32-bit pci dma bus master. ? memory move instructions allow use as a third-party pci bus dma controller. ? high-performance scsi core. ? integrated scripts processor. 1.4.4 ease of use the following features of the LSI53C875 make the device user friendly: ? up to 1 mbyte of add-in memory support for bios and scripts storage. ? direct pci to scsi connection. ? reduced scsi development effort. ? easily adapted to the advanced scsi protocol interface (aspi) or the ansi common access method (cam), with sdms software.
1-8 general description ? compiler-compatible with existing lsi53c7xx and lsi53c8xx family scripts. ? direct connection to pci, and scsi se and differential buses. ? development tools and sample scsi scripts available. ? maskable and pollable interrupts. ? wide scsi, a or p cable, and up to 16 devices are supported. ? three programmable scsi timers: select/reselect, handshake-to- handshake, and general purpose. the time-out period is programmable from 100 s to greater than 25.6 seconds. ? sdms software for complete pc-based operating system support. ? support for relative jumps. ? scsi selected as id bits for responding with multiple ids. 1.4.5 flexibility the following features increase the ?xibility of the LSI53C875: ? high level programming interface (scsi scripts). ? programs local memory and bus flash memory. ? big/little endian support. ? selectable 88 or 536 byte dma fifo for backward compatibility. ? tailored scsi sequences execute from main system ram or internal scripts ram. ? flexible programming interface to tune i/o performance or to adapt to unique scsi devices. ? support for changes in the logical i/o interface de?ition. ? low level access to all registers and all scsi bus signals. ? fetch, master, and memory access control pins. ? separate scsi and system clocks. ? scsi clock doubler bits enable ultra scsi transfer rates with a 40 mhz scsi clock. ? selectable irq pin disable bit. ? 32 additional scratch pad registers. ? ability to route system clock to scsi clock.
LSI53C875 bene?s summary 1-9 1.4.6 reliability the following features enhance the reliability of the LSI53C875: ? 2 kv esd protection on scsi signals. ? typical 300 mv scsi bus hysteresis. ? protection against bus re?ctions due to impedance mismatches. ? controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certi?ation). ? latch-up protection greater than 150 ma. ? voltage feed-through protection (minimum leakage current through scsi pads). ? a high proportion (> 25%) of pins are power and ground. ? power and ground isolation of i/o pads and internal chip logic. ? tolerant technology which provides: active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates. input signal ?tering on scsi receivers improves data integrity, even in noisy cabling environments. ? jtag boundary scan support (LSI53C875j, LSI53C875jb, LSI53C875n only). ? extended pci parity checking and generation (LSI53C875n only). ? extended scsi parity checking. 1.4.7 testability the following features enhance the testability of the LSI53C875: ? access to all scsi signals through programmed i/o. ? scsi loopback diagnostics. ? scsi bus signal continuity checking. ? support for single step mode operation. ? test mode (and tree) to check pin continuity to the board (most package options). ? jtag boundary scan support (LSI53C875j, LSI53C875jb, LSI53C875n only).
1-10 general description
LSI53C875/875e pci to ultra scsi i/o processor 2-1 chapter 2 functional description chapter 2 is divided into the following sections: ? section 2.1, ?csi functional description ? section 2.2, ?esigning an ultra scsi system ? section 2.3, ?refetching scripts instructions ? section 2.4, ?xternal memory interface ? section 2.5, ?ci cache mode ? section 2.6, ?ower management 2.1 scsi functional description the LSI53C875 is composed of three functional blocks: the scsi core , the dma core , and the scripts processor . the LSI53C875 is fully supported by sdms software, a complete software package that supports the lsi logic product line of scsi processors and controllers. the pci bus power management support (LSI53C875e) is discussed section 2.6, ?ower management. 2.1.1 scsi core the scsi core supports the 8-bit or 16-bit data bus. it supports ultra scsi synchronous transfer rates up to 40 mbytes/s, scsi synchronous transfer rates up to 20 mbytes/s, and asynchronous transfer rates up to 10 mbytes/s on a 16-bit wide scsi bus. the scsi core can be programmed with scsi scripts, making it easy to ne tune the system for speci? mass storage devices or scsi-3 requirements.
2-2 functional description the scsi core offers low level register access or a high level control interface. like ?st generation scsi devices, the LSI53C875 scsi core can be accessed as a register oriented device. the ability to sample and/or assert any signal on the scsi bus can be used in error recovery and diagnostic procedures. in support of loopback diagnostics, the scsi core may perform a self-selection and operate as both an initiator and a target. the LSI53C875 scsi core is controlled by the integrated scripts processor through a high level logical interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high speed processor optimized for scsi protocol. 2.1.2 dma core the dma core is a bus master dma device that attaches directly to the industry standard pci bus. the dma core is tightly coupled to the scsi core through the scripts processor, which supports uninterrupted scatter/gather memory operations. the LSI53C875 supports 32-bit memory and automatically supports misaligned dma transfers. a 536-byte fifo allows the LSI53C875 to support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the pci bus interface. 2.1.3 scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores and are executed from 32-bit system ram. the scripts processor executes complex scsi bus sequences independently of the host cpu. the scripts processor can begin a scsi i/o operation in approximately 500 ns. this compares with 2? ms required for traditional intelligent host adapters. algorithms may be designed to tune scsi bus performance, to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2
scsi functional description 2-3 or scsi-3 logical bus de?itions without sacri?ing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. 2.1.4 internal scripts ram the LSI53C875 has 4 kbyte (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the LSI53C875 use the pci bus, as if they were external accesses. the mad5 pin enables the 4 kbyte internal ram. to disable the internal ram, connect a 4.7 k ? resistor between the mad5 pin and v ss . the ram can be relocated by the pci system bios anywhere in 32-bit address space. the ram base address register in pci con?uration space contains the base address of the internal ram. this register is similar to the rom base address register in pci con?uration space. to simplify loading of scripts instructions, the base address of the ram will appear in the scratch register b (scratchb) register when bit 3 of the chip test two (ctest2) register is set. the ram is byte accessible from the pci bus and is visible to any bus mastering device on the bus. external accesses to the ram (by the cpu) follow the same timing sequence as a standard slave register access, except that the target wait-states required drop from 5 to 3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the LSI53C875, see chapter 6, ?nstruction set of the i/o processor. 2.1.5 sdms software: the total scsi solution for users who do not need to develop custom drivers, lsi logic provides a total scsi solution in pc environments with the sdms. sdms software provides bios driver support for hard disk, tape, and removable media peripherals for the major pc-based operating systems.
2-4 functional description sdms software includes a scsi bios to manage all scsi functions related to the device. it also provides a series of scsi device drivers that support most major operating systems. sdms software supports a multithreaded i/o application programming interface (api) for user developed scsi applications. sdms software supports both the aspi and cam scsi software speci?ations. 2.2 designing an ultra scsi system migrating an existing se scsi design from scsi-2 to ultra scsi requires minor software modi?ations as well as consideration for some hardware design guidelines. since ultra scsi is based on existing scsi standards, it can use existing software programs as long as the software is able to negotiate for ultra scsi synchronous transfer rates. in the area of hardware, the primary area of concern in se systems is to maintain signal integrity at high data transfer rates. to assure reliable operation at ultra scsi transfer speeds, follow the system design parameters recommended in the scsi-3 ultra parallel interface standard. chapter 7, ?nstruction set of the i/o processor, contains ultra scsi timing information. in addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate ultra scsi transfers: ? set the ultra enable bit to enable ultra scsi transfers. ? set the tolerant enable bit, bit 7 in the scsi test three (stest3) register whenever the ultra enable bit is set. ? do not extend the sreq/sack ?tering period with scsi test two (stest2), bit 1. 2.2.1 using the scsi clock doubler the LSI53C875 can double the frequency of a 40?0 mhz scsi clock, allowing the system to perform ultra scsi transfers in systems that do not have 80 mhz clock input. this option is user selectable with bit settings in the scsi test one (stest1) , scsi test three (stest3) , and scsi control three (scntl3) registers. at power-on or reset, the doubler is disabled and powered down. follow these steps to use the clock doubler:
prefetching scripts instructions 2-5 step 1. set the sclk doubler enable bit ( scsi test one (stest1) , bit 3). step 2. wait 20 s. step 3. halt the scsi clock by setting the halt scsi clock bit ( scsi test three (stest3), bit 5). step 4. set the clock conversion factor using the scf and ccf ?lds in the scsi control three (scntl3) register. step 5. set the sclk doubler select bit ( scsi test one (stest1) , bit 2). step 6. clear the halt scsi clock bit. 2.3 prefetching scripts instructions when enabled by setting the prefetch enable bit in the dma control (dcntl) register, the prefetch logic in the LSI53C875 fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the dma mode (dmode) register. if the unit cannot perform bursts of at least four dwords, it disables itself. while the LSI53C875 is prefetching scripts instructions, the pci cache line size register value does not have any effect and the read line, read multiple, and write and invalidate commands are not used. the LSI53C875 may ?sh the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. when one of these conditions apply, the contents of the prefetch unit are automatically ?shed. ? on every memory move instruction. the memory move instruction is often used to place modi?d code directly into memory. to make sure that the chip executes all recent modi?ations, the prefetch unit ?shes its contents and loads the modi?d code every time an instruction is issued. to avoid inadvertently ?shing the prefetch unit contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction, refer to chapter 6, ?nstruction set of the i/o processor.
2-6 functional description ? on every store instruction. the store instruction may also be used to place modi?d code directly into memory. to avoid inadvertently ?shing the prefetch unit contents use the no flush option for all store operations that do not modify code within the next 8 dwords. ? on every write to the dma scripts pointer (dsp) . ? on all transfer control instructions when the transfer conditions are met. this is necessary because the next instruction to execute is not the sequential next instruction in the prefetch unit. ? when the prefetch flush bit ( dma control (dcntl) , bit 6) is set. the unit ?shes whenever this bit is set. the bit is self-clearing. 2.3.1 opcode fetch burst capability setting the burst opcode fetch enable bit in the dma mode (dmode) register (0x38) causes the LSI53C875 to burst in the ?st two longwords of all instruction fetches. if the instruction is a memory-to-memory move, the third longword is accessed in a separate ownership. if the instruction is an indirect type, the additional longword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the chip uses two accesses to obtain the four longwords required, in two bursts of two longwords each. note: this feature is only useful if prefetching is disabled. 2.4 external memory interface the LSI53C875 supports up to one megabyte of external memory in binary increments from 16 kbytes, to allow the use of expansion rom for add-in pci cards. the device also supports flash rom updates through the add-in interface and the gpio4 pin (used to control v pp , the power supply for programming external memory). this interface is designed for low speed operations such as downloading instruction code from rom. it is not intended for dynamic activities such as executing instructions. system requirements include the LSI53C875, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k ? pull-down resistors on the mad bus require hc or hct external components to be used. if in-system flash rom
external memory interface 2-7 updates are required, a 7406 (high voltage open collector inverter), an mtd4p05, and several passive components are also needed. the memory size and speed is determined by pull-down resistors on the 8-bit bidirectional memory bus at power-up. the LSI53C875 senses this bus shortly after the release of the reset signal and con?ures the rom base address register and the memory cycle state machines for the appropriate conditions. the external memory interface works with a variety of rom sizes and speeds. an example set of interface drawings is in appendix b, ?xternal memory interface diagram examples. the LSI53C875 supports a variety of sizes and speeds of expansion rom, using pull-down resistors on the mad[3:0] pins. the encoding of pins mad[3:1] allows the user to de?e how much external memory is available to the LSI53C875. table 2.1 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully de?ed in chapter 4, ?ignal descriptions. to use one of the con?urations mentioned above in a host adapter board design, put 4.7 k ? pull-down resistors on the mad pins corresponding to the available memory space. for example, to connect to a 32 kbytes external rom, use pull-downs on mad[3] and mad[2]. if the external memory interface is not used, then no external resistors are table 2.1 external memory support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
2-8 functional description necessary since there are internal pull-ups on the mad bus. the internal pull-up resistors are disabled when external pull-down resistors are detected, to reduce current drain. the LSI53C875 allows the system to determine the size of the available external memory using the expansion rom base address register in pci con?uration space. for more information on how this works, refer to the pci speci?ation or the expansion rom base address register description in chapter 3, ?ci functional description. mad[0] is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to flash memory. the 12 v power supply for flash memory, v pp , is enabled and disabled with the gpio4 pin and the gpio4 control bit. for more information on the gpio4 pin, refer to chapter 4, ?ignal descriptions. 2.5 pci cache mode the LSI53C875 supports the pci speci?ation for an 8-bit cache line size register located in pci con?uration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?xibility in using these commands. for more information on pci cache mode operations, refer to chapter 3, ?ci functional description. 2.5.1 load/store instructions the LSI53C875 supports the load and store instruction type, which simpli?s the movement of data between memory and the internal chip registers. it also enables the chip to transfer bytes to addresses relative to the data structure address (dsa) register. for more information on the load and store instructions, refer to chapter 6, ?nstruction set of the i/o processor.
pci cache mode 2-9 2.5.2 3.3 v/5 v pci interface the LSI53C875 can attach directly to a 3.3 v o ra5vpci interface, due to separate v dd pins for the pci bus drivers. this allows the devices to be used on the universal board recommended by the pci special interest group. 2.5.3 additional access to general purpose pins the LSI53C875 can access the gpio0 and gpio1 general purpose pins through register bits in the pci con?uration space, instead of using the general purpose pin control (gpcntl) register in the operating register space to control these pins. in the lsi logic sdms software, the con?uration bits control pins as the clock and data lines, respectively. to access the gpio[1:0] pins through the con?uration space, connect a 4.7 k ? resistor between the mad[7] pin and v ss . mad[7] contains an internal pull-up that is sensed shortly after chip reset. if the pin is sensed high, gpio[1:0] access is disabled; if it is low, gpio[1:0] access is enabled. additionally, if gpio[1:0] access has been enabled through the mad[7] pin and if gpio0 and/or gpio1 are sensed low after chip reset, gpio[1:0] access is disabled. if gpio[1:0] access through con?uration space is enabled, the gpio0 and gpio1 pins cannot be controlled from the general purpose pin control (gpcntl) and general purpose (gpreg) registers, but are observable from the general purpose (gpreg) register. when gpio[1:0] access is enabled, the serial interface control register at con?uration addresses 0x34?x35 controls the gpio0 and gpio1 pins. for more information on gpio[1:0] access, refer to the serial interface control register description in chapter 3, ?ci functional description. for more information on the gpio pins, see chapter 4, ?ignal descriptions. this does not apply to the LSI53C875e. note: the lsi logic sdms software controls the gpio0 and gpio1 pins using the general purpose pin control (gpcntl) and general purpose (gpreg) registers. therefore, if using sdms software, do not connect a 4.7 k ? resistor between mad[7] and vss.
2-10 functional description 2.5.4 jtag boundary scan testing the LSI53C875j/LSI53C875n/LSI53C875jb include support for jtag boundary scan testing in accordance with the ieee 1149.1 speci?ation with one exception, which is discussed in this section. the device accepts all required boundary scan instructions, including the optional clamp, high-z, and idcode instructions. the LSI53C875j/LSI53C875n/LSI53C875jb use an 8-bit instruction register to support all boundary scan instructions. the data registers included in the device are the boundary data register, the idcode register, and the bypass register. this device can handle a 10 mhz tck frequency for tdo and tdi. due to design constraints, the rst/ pin (system reset) always 3-states the scsi pins when it is asserted. boundary scan logic does not control this action, and this is not compliant with the speci?ation. there are two solutions that resolve this issue: 1. use the rst/ pin as a boundary scan compliance pin. when the pin is deasserted, the device is boundary scan compliant and when asserted, the device is noncompliant. to maintain compliance the rst/ pin must be driven high. 2. when rst/ is asserted during boundary scan testing the expected output on the scsi pins must be a high-z condition, and not what is contained in the boundary scan data registers for the scsi pin output cells. because of package limitations, the LSI53C875j/LSI53C875jb replaces the testin, mac/_testout, big_lit/, and sdirp1 signals with the jtag boundary scan signals. the LSI53C875n includes support for these signals in addition to the jtag pins. 2.5.5 big and little endian support the LSI53C875/LSI53C875n supports both big and little endian byte ordering through pin selection. the LSI53C875j/LSI53C875jb operate in little endian mode only (the big_lit pin is replaced by one of the jtag boundary scan signals). in big endian mode, the ?st byte of an aligned scsi to pci transfer is routed to lane three and succeeding transfers are routed to descending lanes. this mode of operation also applies to data transfers over the add-in rom interface. the byte of data accessed at
pci cache mode 2-11 location 0x0000 from memory is routed to lane three, and the data at location 0x0003 is routed to byte lane 0. in little endian mode, the ?st byte of an aligned scsi to pci transfer is routed to lane zero and succeeding transfers are routed to ascending lanes. this mode of operation also applies to the add-in rom interface. the byte of data accessed at location 0x0000 from memory is routed to lane zero, and the data at location 0x0003 is routed to byte lane 3. the big_lit pin gives the LSI53C875 the ?xibility of operating with either big or little endian byte orientation. internally, in either mode, the actual byte lanes of the dma fifo and registers are not modi?d. the LSI53C875 supports slave accesses in big or little endian mode. when a dword is accessed, no repositioning of the individual bytes is necessary since dwords are addressed by the address of the least signi?ant byte. scripts always uses dwords in 32-bit systems, so compatibility is maintained between systems using different byte orientations. when less than a dword is accessed, individual bytes must be repositioned. internally, the LSI53C875 adjusts the byte control logic of the dma fifo and register decodes to access the appropriate byte lanes. the registers always appear on the same byte lane, but the address of the register is repositioned. big/little endian mode selection has the most effect on individual byte access. internally, the LSI53C875 adjusts the byte control logic of the dma fifo and register decodes to enable the appropriate byte lane. the registers always appear on the same byte lane, but the address of the register is repositioned. data to be transferred between system memory and the scsi bus always starts at address zero and continues through address ? there is no byte ordering in the chip. the ?st byte in from the scsi bus goes to address 0, the second to address 1, etc. going out onto the scsi bus, address zero is the ?st byte out on the scsi bus, address 1 is the second byte, etc. the only difference is that in a little endian system, address 0 is on byte lane 0, and in big endian mode address zero is on byte lane 3. correct scripts are generated if the scripts compiler is run on a system that has the same byte ordering as the target system. any scripts patching in memory must patch the instruction with the byte ordering that the scripts processor expects.
2-12 functional description software drivers for the LSI53C875 should access registers by their logical name (that is, scntl0) rather than by their address. the logical name should be equated to the registers big endian address in big endian mode (scntl0 = 0x03), and its little endian address in little endian mode (scntl0 = 0x00). this way, there is no change to the software when moving from one mode to the other; only the equate statement setting the operating modes needs to be changed. addressing of registers from within a scripts instruction is independent of bus mode. internally, the LSI53C875 always operates in little endian mode. 2.5.6 loopback mode the LSI53C875 loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the scsi test one (stest1) register, the LSI53C875 allows control of all scsi signals whether the chip is operating in initiator or target mode. for more information on this mode of operation refer to the scsi scripts processors programming guide . 2.5.7 parity options the LSI53C875 implements a exible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. table 2.2 de?es the bits that are involved in parity control and observation. table 2.3 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control zero (scntl0) register. table 2.4 describes the options available when a parity error occurs. the LSI53C875n has four additional parity pins for checking incoming data on the pci bus. these pins are assigned to each byte of the pci address/data bus, and work in addition to the par (pci parity) pin. in pci master read or slave write operations, each byte of incoming data on the pci bus is checked against its corresponding parity line, in addition to the normal parity checking against the pci par signal. in pci master write or slave read operations, parity is generated for each byte. this extra parity checking is always enabled for the LSI53C875n. the host system must support these pins. this feature is not register selectable. a parity error on any byte parity pin for pci master read or
pci cache mode 2-13 slave write operations causes a fatal dma interrupt; scripts stops running. mask this interrupt with the ebpe interrupt enable bit, bit 1 in the dma interrupt enable (dien) register. these additional parity pins in no way affect the generation or checking of the pci speci?d parity line. table 2.2 bits used for parity control and generation bit name location description assert satn/ on parity errors scsi control zero (scntl0) , bit 1 when this bit is set, the LSI53C875 automatically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in initiator mode. enable parity checking scsi control zero (scntl0) , bit 3 enables the LSI53C875 to check for parity errors. the LSI53C875 checks for odd parity. this bit also checks for parity errors on the four additional parity pins on the LSI53C875n. assert even scsi parity scsi control one (scntl1) , bit 2 determines the scsi parity sense generated by the LSI53C875 to the scsi bus. disable halt on satn/ or a parity error (target mode only) scsi control one (scntl1) , bit 5 causes the LSI53C875 not to halt operations when a parity error is detected in target mode. enable parity error interrupt scsi interrupt enable zero (sien0) , bit 0 determines whether the LSI53C875 generates an interrupt when it detects a scsi parity error. parity error scsi interrupt status zero (sist0) , bit 0 this status bit is set whenever the LSI53C875 has detected a parity error on the scsi bus. status of scsi parity signal scsi status zero (sstat0) , bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2) , bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity scsi status two (sstat2) , bit 3 and scsi status one (sstat1) , bit 3 these bits re?ct the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register. master parity error enable chip test four (ctest4) , bit 3 enables parity checking during master data phases.
2-14 functional description master data parity error dma status (dstat) , bit 6 set when the LSI53C875 as a master detects that a target device has signaled a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien) , bit 6 by clearing this bit, a master data parity error will not cause irq/ to be asserted, but the status bit will be set in the dma status (dstat) register. extended byte parity error interrupt enable (LSI53C875n only) dma interrupt enable (dien) , bit 1 by clearing this bit, an extended byte parity error will not cause irq/ to be asserted, but the status bit will be set in the dma status (dstat) register. table 2.3 scsi parity control epc aesp description 0 0 does not check for parity errors. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 0 1 does not check for parity errors. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1. key: epc = enable parity checking (bit 3, scsi control zero (scntl0) ). asep = assert scsi even parity (bit 2, scsi control one (scntl1) ). 2. this table only applies when the enable parity checking bit is set. table 2.2 bits used for parity control and generation (cont.) bit name location description
pci cache mode 2-15 2.5.8 dma fifo the dma fifo is 4 bytes wide by 134 transfers deep. the dma fifo is illustrated in figure 2.1 . to assure compatibility with older products in the lsi53c8xx family, the dma fifo size may be set to 88 bytes by setting the dma fifo size bit, bit 5 in the chip test five (ctest5) register. figure 2.1 dma fifo sections table 2.4 scsi parity errors and interrupts dph par description 0 0 halts when a parity error occurs in target or initiator mode and does not generate an interrupt. 0 1 halts when a parity error occurs in target mode and generates an interrupt in the target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is not generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is generated. key: dhp = disable halt on satn/ or parity error (bit 5, scsi control one (scntl1) . par = parity error (bit 0, scsi interrupt enable one (sien1) . 134 transfers deep . . . . . . 32 bytes wide 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0
2-16 functional description 2.5.8.1 data paths the data path through the LSI53C875 is dependent on whether data is being moved into or out of the chip, and whether scsi data is being transferred asynchronously or synchronously. figure 2.2 shows how data is moved to/from the scsi bus in each of the different modes. figure 2.2 LSI53C875 host interface data paths pci interface pci interface pci interface pci interface dma fifo (32 bits x 16) dma fifo (32 bits x 16) dma fifo (32 bits x 16) dma fifo (32 bits x 16) sodl register sidl register sodl register scsi fifo (8 or 16 bits x 16) scsi interface scsi interface sodr register scsi interface scsi interface asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive swide register swide register
pci cache mode 2-17 the following steps determine if any bytes remain in the data path when the chip halts an operation: asynchronous scsi send step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?ant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?ant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2 register, then the least signi?ant byte or the most signi?ant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. synchronous scsi send step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?ant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?ant bits of the dma byte counter (dbc) register from the 10-bit value of
2-18 functional description the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2 register, then the least signi?ant byte or the most signi?ant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. step 3. read bit 6 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the sodr register. if bit 6 is set in the sstat0 or sstat2 register, then the least signi?ant byte or the most signi?ant byte in the sodr register is full, respectively. asynchronous scsi receive step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?ant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?ant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 7 in the scsi status zero (sstat0) and scsi status two (sstat2) register to determine if any bytes are left in the scsi input data latch (sidl) register. if bit 7 is set in the sstat0 or sstat2, then the least signi?ant byte or the most signi?ant byte is full, respectively.
pci cache mode 2-19 step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. synchronous scsi receive step 1. if the dma fifo size is set to 88 bytes, subtract the seven least signi?ant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?ant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bits [7:4] of the scsi status one (sstat1) register and bit 4 of the scsi status two (sstat2) register, the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. 2.5.9 scsi bus interface the LSI53C875 supports both se and differential operation. all scsi signals are active low. the LSI53C875 contains the se output drivers and can be connected directly to the scsi bus. each output is isolated from the power supply to ensure that a powered down LSI53C875 has no effect on an active scsi bus (cmos ?oltage feed-through phenomena). tolerant technology provides signal ?tering at the inputs of sreq/ and sack/ to increase immunity to signal re?ctions.
2-20 functional description 2.5.9.1 differential mode in differential mode, the sdir[15:0], sdirp[1:0], igs, tgs, rstdir, bsydir, and seldir signals control the direction of external differential pair transceivers. the LSI53C875 is placed in differential mode by setting the dif bit, bit 5 of the scsi test two (stest2) register (0x4e). setting this bit 3-states the bsy/, sel/, and rst/ pads so they can be used as pure input pins. in addition to the standard scsi lines, the following signals de?ed in table 2.5 are used during differential operation by the LSI53C875: see figure 2.3 for an example differential wiring diagram, in which the LSI53C875 is connected to the texas instruments sn75976a differential transceiver. the recommended value of the pull-up resistor on the req/, ack/, msg/, c/d/, i/o/, atn/, sd[7:0]/, and sdp0/ lines is 680 ? when the active negation portion of tolerant technology is not enabled. when active negation is enabled, the recommended resistor value on the req/, ack/, sd[7:0]/, and sdp0/ signals is 1.5 k ? . the electrical characteristics of these pins change when active negation is enabled, permitting a higher resistor value. table 2.5 differential mode signal function bsydir, seldir, rstdir active high signals used to enable the differential drivers as outputs for scsi signals bsy/, sel/, and rst/, respectively. sdir[15:0], sdirp[1:0] active high signals used to control direction of the differential drivers for scsi data and parity lines, respectively. igs active high signal used to control direction of the differential driver for initiator group signals atn/ and ack/. tgs active high signal used to control direction of the differential drivers for target group signals msg/, c/d/, i/o/, and req/. diffsens input to the LSI53C875 used to detect the presence of a se device on a differential system. if a logical zero is detected on this pin, then it is assumed that an se device is on the bus and all scsi outputs will be 3-stated to avoid damage to the transceiver.
pci cache mode 2-21 to interface the LSI53C875 to the sn75976a, connect the dir pins, as well as igs and tgs, of the LSI53C875 directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the sn75976a. the scsi bidirectional control and data pins (sd[7:0]/, sdp0/, req/, ack/, msg/, i_o/, c_d/, and atn/) of the LSI53C875 connect to the bidirectional data pins (na) of the sn75976a with a pull-up resistor. the pull-up value should be no lower than the transceiver i ol can tolerate, but not so high as to cause rc timing problems. the three remaining pins, sel/, bsy/, and rst/ are connected to the sn75976a with a pull-down resistor. the pull-down resistors are required when the pins (na) of the sn75976a are con?ured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the LSI53C875 pins (sel/, bsy/, and rst/) and the sn75976a data pins. because the sel/, bsy/, and rst/ pins on the LSI53C875 are inputs only, this con?uration allows for the sel/, bsy/, and rst/ scsi signals to be asserted on the scsi bus. the differential pairs on the scsi bus are reversed when connected to the sn75976a, due to the active low nature of the scsi bus. note: the sn75976a differential transceiver must be used to achieve ultra scsi transfer rates. 8-bit/16-bit scsi and the differential interface in an 8-bit scsi bus, the sd[15:8] pins on the LSI53C875 should be pulled up with a 1.5 k ? resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left ?ating. in the LSI53C875j and LSI53C875jb, the sdirp1 pin is replaced by the tck jtag signal. if the device is used in a wide differential system, use the sdirp0 pin to control the direction of the differential transceiver for both the sp0 and sp1 signals. the sdirp0 signal is capable of driving both direction inputs from a transceiver.
2-22 functional description figure 2.3 differential wiring diagram lsi53c8xx seldir bsydir rstdir sel/ bsy/ rst/ req/ ack/ msg/ c/d/ i/o/ atn/ tgs igs sd[8:15]/ sdp1/ sdirp0 sdir7 sdir6 sdir5 sdir4 sdir3 sdir2 sdir1 sdir0 sdp0/ sd7/ sd6/ sd5/ sd4/ sd3/ sd2/ sd1/ sd0/ diffsens 1.5 k 1.5 k ? vdd vdd 1.5 k ? 1.5 k ? vdd 1.5 k ? vdd vdd 1.5 k ? sn75976a cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re sel/ seldir bsydir rstdir req/ bsy/ rst/ ack/ msg/ c_d/ i_o/ atn/ vdd 1.5 k ? diffsens schottky diode diffsens (pin 21) ? sel scsi bus +sel ? bsy +bsy ? rst (42) +rst ? req +req ? ack +ack ? msg +msg ? c/d +c/d ? i/o +i/o ? at n +atn 1b+ 1b ? 2b+ 2b ? 3b+ 3b ? 4b+ 4b ? 5b+ 5b ? 6b+ 6b ? 7b+ 7b ? 8b+ 8b ? 9b+ 9b ? (41) (34) (33) (38) (37) (46) (45) (36) (35) (40) (39) (44) (43) (48) (47) (30) (29) sn75976a cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re ? db0 +db0 ? db1 +db1 ? db2 (4) +db2 ? db3 +db3 ? db4 +db4 ? db5 +db5 ? db6 +db6 ? db7 +db7 ? dbp +dbp 1b+ 1b ? 2b+ 2b ? 3b+ 3b ? 4b+ 4b ? 5b+ 5b ? 6b+ 6b ? 7b+ 7b ? 8b+ 8b ? 9b+ 9b ? (3) (6) (5) (8) (7) (10) (9) (12) (11) (14) (13) (16) (15) (18) (17) (20) (19) diffsens diffsens sdir0 sdir1 sdir2 sdir3 sdir4 sdir5 sdir6 sdir7 sdirp0 sd0 / sd1 / sd2/ sd3/ sd4 / sd5 / sd6/ sd7/ sdp0/ 1.5 k
pci cache mode 2-23 2.5.9.2 terminator networks the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends. no system should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of accommodating terminators. there should be a means of disabling termination. se cables can use a 220 ? pull-up to the terminator power supply (term power) line and a 330 ? pull-down to ground. because of the high-performance nature of the LSI53C875, regulated (or active) termination is recommended. figure 2.4 shows a unitrode active terminator. for additional information, refer to the scsi-2 speci?ation. tolerant technology active negation can be used with either termination network. note: if the LSI53C875 is to be used in a design with only an 8-bit scsi bus, all 16 data lines still must be terminated or pulled high. active termination is required for ultra scsi synchronous transfers.
2-24 functional description figure 2.4 regulated termination terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 terml10 terml11 terml12 terml13 terml14 terml15 terml16 terml17 terml18 sd0 (j1.40) sd1 (j1.41) sd2 (j1.42) sd3 (j1.43) sd4 (j1.44) sd5 (j1.45) sd6 (j1.46) sd7 (j1.47) sdp (j1.48) atn (j1.55) bsy (j1.57) ack (j1.58) rst (j1.59) msg (j1.60) sel (j1.61) c/d (j1.62) req (j1.63) i/o (j1.64) 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 19 disconnect reg_out 2 2.85 v uc5601qp c1 c2 notes: ? c1 - 10 f smt ? c2 - 0.1 f smt ? c3 - 2.2 f smt ? j1 - 68-pin, high density ? connector terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 sd15 (j1.38) sd14 (j1.37) sd13 (j1.36) sd12 (j1.35) sd11 (j1.68) sd10 (j1.67) sd9 (j1.66) sd8 (j1.65) sdp1 (j1.39) 10 9 8 7 3 2 1 16 15 reg_out 14 uc5603dp c3 6 disconnect
pci cache mode 2-25 2.5.10 select/reselect during selection/reselection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this situation may occur when a scsi controller (operating in the initiator mode) tries to select a target and is reselected by another. the select scripts instruction has an alternate address to which the scripts will jump when this situation occurs. the analogous situation for target devices is being selected while trying to perform a reselection. once a change in operating mode occurs, the initiator scripts should start with a set initiator instruction or the target scripts should start with a set target instruction. the selection and reselection enable bits ( scsi chip id (scid) bits 5 and 6, respectively) should both be asserted so that the LSI53C875 may respond as an initiator or as a target. if only selection is enabled, the LSI53C875 cannot be reselected as an initiator. there are also status and interrupt bits in the scsi interrupt status zero (sist0) and scsi interrupt enable zero (sien0) registers, respectively, indicating that the LSI53C875 has been selected (bit 5) and reselected (bit 4). 2.5.11 synchronous operation the LSI53C875 can transfer synchronous scsi data in both the initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it may be loaded by the cpu before scripts execution begins, from within scripts using a table indirect i/o instruction, or with a read-modify-write instruction. the LSI53C875 can receive data from the scsi bus at a synchronous transfer period as short as 50 ns, regardless of the transfer period used to send data. the LSI53C875 can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the LSI53C875 can send synchronous data at intervals as short as 50 ns for ultra scsi, 100 ns for fast scsi, and 200 ns for scsi-1.
2-26 functional description 2.5.11.1 determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the LSI53C875. following is a brief description of the bits. figure 2.5 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. figure 2.5 determining the synchronous transfer rate 2.5.11.2 scsi control three (scntl3) register, bits [6:4] (scf[2:0]) the scf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received; this rate must not exceed 80 mhz. the receive rate of synchronous scsi data is one-fourth of the scf divider output. for sclk scf divider ccf divider synchronous divider asynchronous scsi logic divide by 4 scf2 scf1 scf0 scf divisor 0011 0 1 0 1.5 0112 1003 0003 1014 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 ccf2 ccf1 ccf0 divisor 0011 0 1 0 1.5 0112 1003 0003 1014 example (8-bit scsi bus): sclk = 80 mhz, scf = 1 ( 1) , xferp = 4 ( 4), ccf = 5 ( 4) this point must not exceed 80 mhz receive clock send clock (to scsi bus) this point must not exceed 25 mhz = (80 1) 4 = 20 mbytes/s scsi receive rate = (sclk scf) 4 = (80 1) 4 = 20 mbytes/s clock doubler scsi send rate = (sclk scf) xferp
pci cache mode 2-27 example, if sclk is 80 mhz and the scf value is set to divide by two, then the maximum rate at which data can be received is 10 mhz (80/(2*4) = 10). 2.5.11.3 scsi control three (scntl3) register, bits [2:0] (ccf[2:0]) the ccf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the table. 2.5.11.4 scsi transfer (sxfer) register, bits [7:5] (tp[2:0]) the tp[2:0] divider bits determine the scsi synchronous transfer period when sending synchronous scsi data in either initiator or target mode. this value further divides the output from the scf divider. 2.5.11.5 achieving optimal scsi send rates to achieve optimal synchronous scsi send timings, the scf divisor value should be set high, to divide the clock as much as possible before presenting the clock to the tp divider bits in the scsi transfer (sxfer) register. the tp[2:0] divider value should be as low as possible. for example, with an 80 mhz clock to achieve a 20 mbytes/s ultra scsi send rate, the scf bits can be set to divide by 1 (001) and the tp bits to divide by 4 (000). to set for a 10 mbytes/s send rate for fast scsi- 2, the scf bits can be set to divide by 2 (011) and the tp bits set to divide by 4 (000). 2.5.12 ultra scsi synchronous data transfers ultra scsi is an extension of current fast scsi-2 synchronous transfer speci?ations. it allows synchronous transfer periods to be negotiated down as low as 50 ns, which is half the 100 ns period allowed under fast scsi-2. this will allow a maximum transfer rate of 40 mbytes/s on a 16-bit scsi bus. the LSI53C875 requires an 80 mhz scsi clock input to perform ultra scsi transfers. in addition, the following bit values affect the chips ability to support ultra scsi synchronous transfer rates: ? clock conversion factor bits, scsi control three (scntl3) register bits [2:0] and synchronous clock conversion factor bits, scsi control three (scntl3) register bits [6:4]. these ?lds now support
2-28 functional description a value of 101 (binary), allowing the sclk frequency to be divided down by 4. this allows systems using an 80 mhz clock or the internal clock doubler to operate at fast scsi-2 transfer rates as well as ultra scsi rates, if needed. ? ultra mode enable bit, scsi control three (scntl3) register bit 7. setting this bit enables ultra scsi synchronous transfers in systems that have an 80 mhz clock or use the internal scsi clock doubler. 2.5.13 interrupt handling the scripts processors in the LSI53C875 perform most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the LSI53C875. 2.5.13.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the LSI53C875 asserts the interrupt request (irq/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.5.13.2 registers the registers in the LSI53C875 that are used for detecting or de?ing interrupts are the interrupt status (istat) , scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , dma status (dstat) , scsi interrupt enable zero (sien0) , scsi interrupt enable one (sien1) , dma control (dcntl) , and dma interrupt enable (dien) . istat the istat register is the only register that can be accessed as a slave during scripts operation. therefore it is the register that is polled when polled interrupts are used. it is also the ?st register that should be read when the irq/ pin has been asserted in association with
pci cache mode 2-29 a hardware interrupt. the intf (interrupt-on-the-fly) bit should be the ?st interrupt serviced. it must be written to one to be cleared. this interrupt must be cleared before servicing any other interrupts. if the sip bit in the interrupt status (istat) register is set, then a scsi-type interrupt has occurred and the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read. if the dip bit in the interrupt status (istat) register is set, then a dma-type interrupt has occurred and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. sist0 and sist1 the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers contain the scsi-type interrupt bits. reading these registers determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition. if the LSI53C875 is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. if the LSI53C875 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. because of this, the dma fifo empty (dfe) bit in dma status (dstat) should be checked. if this bit is cleared, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing. the clf bit is bit 2 in chip test three (ctest3) . the csf bit is bit 1 in scsi test three (stest3) . dstat the dma status (dstat) register contains the dma-type interrupt bits. reading this register determines which condition or conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7 in dstat, dfe, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read. dma interrupts ?sh neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dma status (dstat) register should be checked after any dma interrupt.
2-30 functional description if the dfe bit is cleared, then the fifos must be cleared by setting the clf (clear dma fifo) and csf (clear scsi fifo) bits, or ?shed by setting the flf (flush dma fifo) bit. sien0 and sien1 the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) . dien the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . dcntl when bit 1 in this register is set, the irq/ pin is not asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but merely masked at the pin. clearing this bit when an interrupt is pending immediately causes the irq/ pin to assert. as with any register other than istat, this register cannot be accessed except by a scripts instruction during scripts execution. 2.5.13.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes scripts to stop running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking is discussed section 2.5.13.4, ?asking. all dma interrupts (indicated by the dip bit in istat and one or more bits in dma status (dstat) being set) are fatal. some scsi interrupts (indicated by the sip bit in the istat and one or more bits in scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) being set) are nonfatal. when the LSI53C875 is operating in initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake-to-handshake timer expired (hth) interrupts are nonfatal. when operating in target mode cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are nonfatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scsi control one (scntl1) register to con?ure the chips
pci cache mode 2-31 behavior when the satn/ interrupt is enabled during target mode operation. the interrupt-on-the-fly interrupt is also nonfatal, since scripts can continue when it occurs. the reason for nonfatal interrupts is to prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the LSI53C875 has been selected or reselected (sel or rsl set), when the initiator asserts atn (target mode: satn/ active), or when the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high-level scripts operation. 2.5.13.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts can be masked by clearing bits in the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) (for scsi interrupts) registers or dma interrupt enable (dien) (for dma interrupts) register. how the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, the scripts do not stop, the appropriate bit in the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) is still set, the sip bit in the interrupt status (istat) is not set, and the irq/ pin is not asserted. see section 2.5.13.3, ?atal vs. nonfatal interrupts, for a list of the nonfatal interrupts. if a fatal interrupt is masked and that condition occurs, then the scripts still stop, the appropriate bit in the dma status (dstat) , scsi interrupt status zero (sist0) ,or scsi interrupt status one (sist1) register is set, and the sip or dip bits in the interrupt status (istat) is set, but the irq/ pin is not asserted. when the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, scripts halts and the system will never know it unless it times out and checks the istat after a certain period of inactivity.
2-32 functional description if you are polling the istat instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the interrupt status (istat) inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted does not cause irq/ to be deasserted. 2.5.13.5 stacked interrupts the LSI53C875 will stack interrupts if they occur one after the other. if the sip or dip bits in the istat register are set (?st level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) . when the ?st level of interrupts are cleared, all the interrupts that came in afterward move into the sist0, sist1, and dstat. after the ?st interrupt is cleared by reading the appropriate register, the irq/ pin is deasserted for a minimum of three clks; the stacked interrupts move into the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) ,or dma status (dstat) ; and the irq/ pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in sist0, but does not assert the irq/ pin. since no interrupt is generated, future interrupts move right into the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but will not be stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set).
pci cache mode 2-33 as previously mentioned, dma interrupts do not attempt to ?sh the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these ?ocked out scsi interrupts are posted as soon as the dma fifo is empty. 2.5.13.6 halting in an orderly fashion when an interrupt occurs, the LSI53C875 attempts to halt in an orderly fashion. ? if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dma scripts pointer (dsp) points to the next instruction since it is updated when the current instruction is fetched. ? if the dma direction is a write to memory and a scsi interrupt occurs, the LSI53C875 attempts to ?sh the dma fifo to memory before halting. under any other circumstances only the current cycle is completed before halting, so the dfe bit in dstat should be checked to see if any data remains in the dma fifo. ? scsi sreq/sack handshakes that have begun are completed before halting. ? the LSI53C875 attempts to clean up any outstanding synchronous offset before halting. ? in the case of transfer control instructions, once instruction execution begins it continues to completion before halting. ? if the instruction is a jump/call when/if , the dma scripts pointer (dsp) is updated to the transfer address before halting. ? all other instructions may halt before completion. 2.5.13.7 sample interrupt service routine the following is a sample of an interrupt service routine for the LSI53C875. it can be repeated during polling or should be called when the irq/ pin is asserted during hardware interrupts.
2-34 functional description 1. read interrupt status (istat) . 2. if the intf bit is set, it must be written to a one to clear this status. 3. if only the sip bit is set, read scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 tell which scsi interrupts occurred and determine what action is required to service the interrupts. 4. if only the dip bit is set, read the dma status (dstat) to clear the interrupt condition and get the dma interrupt status. the bits in dstat tell which dma interrupts occurred and determine what action is required to service the interrupts. 5. if both the sip and dip bits are set, read scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clk delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the interrupt service routine. it is recommended that the dma interrupt be serviced before the scsi interrupt, because a serious dma interrupt condition could in?ence how the scsi interrupt is acted upon. 6. when using polled interrupts, go back to step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the ?st interrupt was cleared. when using hardware interrupts, the irq/ pin is asserted again if there are any stacked interrupts. this should cause the system to re-enter the interrupt service routine. 2.5.14 chained block moves since the LSI53C875 has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register are used to facilitate these situations. the chained block move instruction is illustrated in figure 2.6 .
pci cache mode 2-35 figure 2.6 block move and chained block move instructions chmov 5, 3 when data_out moves ve bytes from address 0x03 in the host memory to the scsi bus. bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the low-order byte of the scsi output data latch (sodl) register and is combined with the ?st byte of the following move instruction. move 5, 9 when data_out moves ve bytes from address 0x09 in the host memory to the scsi bus. 2.5.14.1 wide scsi send bit the wss bit is set whenever the scsi controller is sending data (data-out for initiator or data-in for target) and the controller detects a partial transfer at the end of a chained block move scripts instruction (this ?g is not set if a normal block move instruction is used). under this condition, the scsi controller does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register and the wss ?g is set. the hardware uses the wss ?g to determine what behavior must occur at the start of the next data 0x03 0x02 0x01 0x00 0x07 0x06 0x05 0x04 0x0b 0x0a 0x09 0x08 0x0f 0x0e 0x0d 0x0c 0x13 0x12 0x11 0x10 0x04 0x03 0x06 0x05 0x09 0x07 0x0b 0x0a 0x0d 0x0c 32 bits 16 bits host memory scsi bus 00 04 08 0c 10
2-36 functional description send transfer. when the wss ?g is set at the start of the next transfer, the ?st byte (the high-order byte) of the next data send transfer is ?arried with the stored low-order byte in the sodl register; and the two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the ?g is automatically cleared when the ?arried word is sent. the ?g can alternately be cleared through scripts or by the microprocessor. also, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.5.14.2 wide scsi receive bit the wsr bit is set whenever the scsi controller is receiving data (data-in for initiator or data-out for target) and the controller detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high-order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is temporarily stored in the scsi wide residue (swide) register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the bit can alternatively be cleared by the microprocessor or through scripts. the bit can also be used by the microprocessor or scripts for error detection and recovery purposes. 2.5.14.3 swide register this register stores data for partial byte data transfers. for receive data, the scsi wide residue (swide) register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.5.14.4 sodl register for send data, the low-order byte of the scsi output data latch (sodl) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually ?arried with the ?st byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command.
pci cache mode 2-37 2.5.14.5 chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data-in for initiator or data-out for target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction, the wsr ?g is set. the high-order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the contents of the swide register should be the ?st byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the scsi wide residue (swide) register is one of the bytes in the byte count. if the wsr bit is clear when a receive data chained block move instruction is executed, the data transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or clear, when a normal block move instruction is executed, the contents of the scsi wide residue (swide) register are ignored and the transfer takes place normally. for ? consecutive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves. for send data (data-out for initiator or data-in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the scsi output data latch (sodl) register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of ?e bytes (and wss is not previously set), ?e bytes are transferred out of memory to the scsi controller, four bytes are transferred from the scsi controller across the scsi bus, and one byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register waiting to be married with the ?st byte of the next block move instruction. regardless of whether a chained block move or normal
2-38 functional description block move instruction is used, if the wss bit is set at the start of a data send command, the ?st byte of the data send command is assumed to be the high-order byte and is ?arried with the low-order byte stored in the lower byte of the scsi output data latch (sodl) register before the two bytes are sent across the scsi bus. for ? consecutive wide data send block move commands, the ?st through the (nth 1) block move instructions should be chained block moves. 2.6 power management the LSI53C875e complies with the pci bus power management interface speci?ation, revision 1.0. the pci function power states d0, d1, d2, and d3 are de?ed in that speci?ation. d0 and d3 are required by speci?ation, and d1 and d2 are optional. d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. a function that is powered off is said to be in the d3cold power state. the power states for the scsi function are independently controlled through two power state bits that are located in the pci con?uration space register 0x44. the bits are encoded as: power states d1 and d2 are not discussed because they have not been implemented as a new feature. the power states d0 and d3 are described below in conjunction with each scsi function. power state actions are separate for each function. 2.6.1 power state d0 power state d0 is the maximum power state and is the power-up default state for each function. 00b d0 01b reserved 10b reserved 11b d3
power management 2-39 2.6.2 power state d3 power state d3 is the minimum power state, which includes subsettings called d3hot and d3cold. the devices are considered to be in power state d3cold when power is removed from them. d3cold can transition to d0 by applying v cc and resetting the device. d3hot allows the device to transition to d0 using software. to obtain power reduction in d3hot, the scsi clock and the scsi clock doubler phase lock loop (pll) are disabled. furthermore, the functions soft reset is continually asserted while in power state d3, which clears all pending interrupts and 3-states the scsi bus. in addition, the functions pci command register is cleared.
2-40 functional description
LSI53C875/875e pci to ultra scsi i/o processor 3-1 chapter 3 pci functional description this chapter is divided into the following sections: ? section 3.1, ?ci addressing ? section 3.2, ?ci cache mode ? section 3.3, ?on?uration registers 3.1 pci addressing there are three types of pci-de?ed address space: ? con?uration space ? memory space ? i/o space the con?uration space is a contiguous 256 x 8-bit set of addresses dedicated to each ?lot or ?tub on the bus. decoding c_be/[3:0] determines if a pci cycle is intended to access con?uration register space. the idsel bus signal is a ?hip select that allows access to the con?uration register space only. a con?uration read/write cycle without idsel is ignored. the eight lower order addresses select a speci? 8-bit register. ad[10:8] are decoded as well, but they must be zero or the LSI53C875 does not respond. according to the pci speci?ation, ad[10:8] are reserved for multifunction devices. the host processor uses the pci con?uration space to initialize the LSI53C875. the lower 128 bytes of the LSI53C875 con?uration space holds system parameters while the upper 128 bytes map into the LSI53C875 operating registers. for all pci cycles except con?uration cycles, the LSI53C875 registers are located on the 256-byte block boundary de?ed by the base
3-2 pci functional description address assigned through the con?ured register. the LSI53C875 operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. at initialization time, each pci device is assigned a base address (in the case of the LSI53C875, the upper 24 bits of the address are selected) for memory and i/o accesses. on every access, the LSI53C875 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if the upper 24 bits match, the access is for the LSI53C875 and the low-order eight bits de?e the register to be accessed. a decode of c_be/[3:0] determines which registers and what type of access is to be performed. the pci speci?ation de?es memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C875. base address one (memory) determines which 256-byte memory area this device occupies. the pci speci?ation de?es i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the LSI53C875. base address zero (i/o) determines which 256-byte i/o area this device occupies. 3.1.1 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be/[3:0] lines during the address phase. pci bus command encoding and types appear in table 3.1 .
pci addressing 3-3 3.1.1.1 i/o read command the i/o read command reads data from an agent mapped in i/o address space. all 32 address bits are decoded. 3.1.1.2 i/o write command the i/o write command writes data to an agent when mapped in i/o address space. all 32 address bits are decoded. table 3.1 pci bus commands and encoding types c_be[3:0] command type supported as master supported as slave 0000 special interrupt acknowledge no no 0001 special cycle no no 0010 i/o read cycle yes yes 0011 i/o write cycle yes yes 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 memory read yes yes 0111 memory write yes yes 1000 reserved n/a n/a 1001 reserved n/a n/a 1010 con?uration read no yes 1011 con?uration write no yes 1100 memory read multiple yes 1 no (defaults to 0110) 1101 dual address cycle no no 1110 memory read line yes 2 no (defaults to 0110) 1111 memory write and invalidate yes 3 no (defaults to 0111) 1. this operation is selectable by bit 2 in the dma mode (dmode) operating register. 2. this operation is selectable by bit 3 in the dma mode (dmode) operating register. 3. this operation is selectable by bit 0 in the chip test three (ctest3) operating register.
3-4 pci functional description 3.1.1.3 memory read the memory read command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 3.1.1.4 memory read multiple the memory read command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 3.1.1.5 memory read line the memory read command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 3.1.1.6 memory write the memory write command writes data to an agent when mapped in memory address space. all 32 address bits are decoded. 3.1.1.7 memory write and invalidate the memory write command writes data to an agent when mapped in memory address space. all 32 address bits are decoded. 3.2 pci cache mode the LSI53C875 supports the pci speci?ation for an 8-bit cache line size register located in the pci con?uration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?xibility in using these commands. 3.2.1 support for pci cache line size register the LSI53C875 supports the pci speci?ation for an 8-bit cache line size register in pci con?uration space. it can sense and react to nonaligned addresses corresponding to cache line boundaries.
pci cache mode 3-5 3.2.2 selection of cache line size the cache logic selects a cache line size based on the values for the burst size in the dma mode (dmode) register, bit 2 in the chip test five (ctest5) register, and the pci cache line size register. note: the LSI53C875 does not automatically use the value in the pci cache line size register as the cache line size value. the chip scales the value of the cache line size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128), compares this value to the burst size de?ed by the values of the dma mode (dmode) register and bit 2 of the chip test five (ctest5) register, then selects the smallest as the value for the cache line size. the LSI53C875 uses this value for all burst data transfers. 3.2.3 alignment the LSI53C875 uses the calculated line size value to monitor the current address for alignment to the cache line size. when it is not aligned, the chip attempts to align to the cache boundary by using a ?mart aligning scheme. this means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no over?w. this process is a stepping mechanism that steps up to the highest possible burst size based on the current address. the stepping process begins a ta4dword boundary. the LSI53C875 will ?st try to align to a 4 dword boundary (0x00, 0x010, 0x020, etc.) by using single dword transfers (no bursting). once this boundary is reached the chip evaluates the current alignment to various burst sizes allowed, and selects the largest possible as the next burst size, while not exceeding the cache line size. the chip then issues this burst, and reevaluates the alignment to various burst sizes, again selecting the largest possible while not exceeding the cache line size, as the next burst size. this stepping process continues until the chip reaches the cache line size boundary or runs out of data. once a cache line boundary is reached, the chip uses the cache line size as the burst size from then on, except in the case of multiples (explained below). the alignment process is ?ished at this point.
3-6 pci functional description example: cache line size - 16, current address = 0x01 the chip is not aligned to a 4 dword cache boundary (the stepping threshold), so it issues four single dword transfers (the ?st is a 3-byte transfer). at address 0x10, the chip is aligned to a 4 dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. so, the part issues a burst of 4. at this point, the address is 0x20, and the chip evaluates that it is aligned not only t oa4dword boundary, but also to an 8 dword boundary. it selects the highest, 8, and bursts 8 dwords. at this point, the address is 0x40, which is a cache line size boundary. alignment stops, and the burst size from then on is switched to 16. 3.2.4 memory move misalignment the LSI53C875 does not operate in a cache alignment mode when a memory move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. for example, if the read address is 0x21f and the write address is 0x42f, and the cache line size is 8, the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. the read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. in this situation, the chip does not align to cache boundaries and operates as an lsi53c825. 3.2.5 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in pci con?uration space. the LSI53C875 enables memory write and invalidate cycles when bit 0 in the chip test three (ctest3) register (wrie) and bit 4 in the pci command register are set. when the following conditions are met, memory write and invalidate commands are issued: 1. the clse bit (cache line size enable, bit 7, dma control (dcntl) register), wrie bit (write and invalidate enable, bit 0, chip test three (ctest3) register), and pci con?uration command register, bit 4 are set.
pci cache mode 3-7 2. the cache line size register contains a legal burst size (2, 4, 8, 16, 32, 64, or 128) value and that value must be less than or equal to the dma mode (dmode) burst size. 3. the chip has enough bytes in the dma fifo to complete at least one full cache line burst. 4. the chip is aligned to a cache line boundary. when these conditions are met, the LSI53C875 issues a write and invalidate command instead of a memory write command during all pci write cycles. multiple cache line transfers the write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size speci?d in the revision 2.1 of the pci speci?ation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being that determined from the dma mode (dmode) burst size bits and chip test five (ctest5) , bit 2. if multiple cache line size transfers are not desired, set the dma mode (dmode) burst size to exactly the cache line size and the chip only issues single cache line transfers. after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the dma mode (dmode) burst size. the most likely scenario of this scheme is that the chip selects the dma mode (dmode) burst size after alignment, and issues bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip ?ishes the transfer with this burst size. 3.2.5.1 latency in accordance with the pci speci?ation, the latency timer is ignored when issuing a write and invalidate command such that when a latency time-out occurs, the LSI53C875 continues to transfer up to a cache line boundary. at that point, the chip relinquishes the bus, and ?ishes the
3-8 pci functional description transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. pci target retry during a write and invalidate transfer, if the target device issues a retry (stop with no trdy, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to ?ish the transfer on another bus ownership. the chip issues another write and invalidate command on the next ownership, in accordance with the pci speci?ation. pci target disconnect during a write and invalidate transfer, if the target device issues a disconnect the LSI53C875 relinquishes the bus and immediately tries to ?ish the transfer on another bus ownership. the chip does not issue another write and invalidate command on the next ownership unless the address is aligned. 3.2.6 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a single memory cycle. the read line function in the LSI53C875 takes advantage of the pci 2.1 speci?ation regarding issuing this command. the functionality of the enable read line bit (bit 3in dma mode (dmode)) has been modi?d to more resemble the write and invalidate mode in terms of conditions that must be met before a read line command is issued. however, the read line option operates exactly like the previous lsi53c8xx chips when cache mode has been disabled by a clse bit reset or when certain conditions exist in the chip (explained below). the read line mode is enabled by setting bit 3 in the dma mode (dmode) register. if cache mode is disabled, read line commands are issued on every read data transfer, except opcode fetches, as in previous lsi53c8xx chips. if cache mode is enabled, a read line command is issued on all read cycles, except opcode fetches, when the following conditions are met:
pci cache mode 3-9 1. the clse (cache line size enable, bit 7, dma control (dcntl) register) and erl (enable read line, bit 3, dma mode (dmode) register) bit are set. 2. the cache line size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. 3. the number of bytes to be transferred at the time a cache boundary has been reached is equal to or greater than the dma mode (dmode) burst size. 4. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command. 3.2.7 memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the LSI53C875 supports pci read multiple functionality and issues read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 (ermp) of the dma mode (dmode) register. if cache mode is enabled, a read multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: 1. the clse bit (cache line size enable, bit 7, dma control (dcntl) register) and the ermp bit (enable read multiple, bit 2, dma mode (dmode) register) are set. 2. the cache line size register contains a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. 3. the number of bytes to be transferred at the time a cache boundary is reached must be at least twice the full cache line size. 4. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read multiple command instead of a memory read during all pci read cycles.
3-10 pci functional description burst size selection the read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to be read is a multiple of the cache line size speci?d in revision 2.1 of the pci speci?ation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being determined from the dma mode (dmode) burst size bits and chip test five (ctest5) , bit 2. read multiple with read line enabled when both the read multiple and read line modes are enabled, the read line command is not issued if the above conditions are met. instead, a read multiple command is issued, even though the conditions for read line are met. if the read multiple mode is enabled and the read line mode is disabled, read multiple commands are issued if the read multiple conditions are met. unsupported pci commands the LSI53C875 does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. it never generates these commands as a master.
con?uration registers 3-11 3.3 con?uration registers the con?uration registers are accessible only by the system bios during pci con?uration cycles. the lower 128 bytes hold con?uration data while the upper 128 bytes hold the LSI53C875 operating registers, which are described in chapter 5, ?csi operating registers. these registers are accessed by scripts or the host processor, if necessary. note: the con?uration register descriptions provide general information only, to indicate which pci con?uration addresses are supported in the LSI53C875. for detailed information, refer to the pci speci?ation. table 3.2 shows the pci con?uration registers implemented by the LSI53C875/875e. all pci-compliant devices, such as the LSI53C875, must support the vendor id , device id , command , and status registers. support of other pci-compliant registers is optional. in the LSI53C875, registers that are not supported are not writable and returns all zeros when read. only those registers and bits that are currently supported by the LSI53C875 are described in this chapter. for more detailed information on pci registers, please see the pci speci?ation.
3-12 pci functional description table 3.2 pci con?uration register map 31 16 15 0 device id vendor id 0x00 status command 0x04 class code revision id 0x08 not supported header type latency timer cache line size 0x0c base address zero (i/o) 1 1. i/o base is supported. 0x10 base address one (memory) 2 2. memory base is supported. 0x14 base address two (memory) scripts ram 3 3. this register powers up enabled and can be disabled by pull-down resistors on the mad5 pin. 0x18 not supported 0x1c not supported 0x20 not supported 0x24 reserved 0x28 subsystem id (ssid) subsystem vendor id (ssvid) 0x2c expansion rom base address 4 4. if expansion memory is enabled through pull-down resistors on the mad[7:0] bus. note: addresses 0x40?x7f are not de?ed for the LSI53C875. addresses 0x48?x7f are not de?ed for the LSI53C875e. all unsupported registers are not writable and return all zeros when read. reserved registers also return zeros when read. 0x30 reserved capabilities pointer 0x34 reserved 0x38 max_lat min_gnt interrupt pin interrupt line 0x3c power management capabilities next item pointer capability id 0x40 data bridge support exten- sions (pmcsr_bse) power management control/status 0x44
con?uration registers 3-13 register: 0x00 vendor id read only vid vendor id [15:0] this 16-bit register identi?s the manufacturer of the device. the vendor id is 0x1000. register: 0x02 device id read only did device id [15:0] this 16-bit register identi?s the particular device. the LSI53C875 device id is 0x000f. register: 0x04 command read/write the command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the LSI53C875 is logically disconnected from the pci bus for all accesses except con?uration accesses. in the LSI53C875, bits 3, 5, 7, and 9 are not implemented. bits 10 through 15 are reserved. 15 0 vid 1111000000000000 15 0 did 0000000000000000 15 9 8 7 6 5 4 3 2 1 0 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 00 00
3-14 pci functional description r reserved [15:9] serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is cleared. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 enable parity error response 6 this bit allows the LSI53C875 to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled. the LSI53C875 always generates parity for the pci bus. r reserved 5 wie write and invalidate mode 4 this bit allows the LSI53C875 to generate memory write and invalidate commands on the pci bus. the wie bit in the dma control (dcntl) register must also be set for the device to generate write and invalidate commands. for more information on these conditions, refer to the section section 3.2.5, ?emory write and invalidate command. to enable write and invalidate mode, set bit 0 in the chip test three (ctest3) register (operating register set). r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the LSI53C875 to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the LSI53C875 to behave as a bus master. the LSI53C875 must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the LSI53C875 to respond to memory space accesses. a value of zero disables the device response. a value of one allows the LSI53C875 to respond to memory space accesses at the address spec- i?d by base address one (memory) .
con?uration registers 3-15 eis enable i/o space 0 this bit controls the LSI53C875 response to i/o space accesses. a value of zero disables the device response. a value of one allows the LSI53C875 to respond to i/o space accesses at the address speci?d in base address zero (i/o) . register: 0x06 status read/write the status register records status information for pci bus related events. in the LSI53C875, bits 0 through 3 are reserved and bits 5, 6, 7, and 11 are not implemented by the LSI53C875. reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is reset whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the LSI53C875 whenever it detects a data parity error, even if parity error handling is disabled. sse signaled system error 14 this bit is set whenever a device asserts the serr/ signal. rma master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. all master devices should implement this bit. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. all master devices should implement this bit. 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt[1:0] dpr rnc r 0000 0000 0 0 01 0 0 0 0
3-16 pci functional description r reserved 11 dt[1:0] devsel/timing [10:9] these bits encode the timing of devsel/. these are encoded as these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?uration read and con?uration write. the LSI53C875 supports a value of 0b01. dpr data parity reported 8 this bit is set when the following conditions are met: ? the bus agent asserted perr/ itself or observed perr/ asserted. ? the agent setting this bit acted as the bus master for the operation in which the error occurred. ? the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities 4 this bit is set to indicate a list of extended capabilities such as pci power management. this bit is read only. r reserved [3:0] 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
con?uration registers 3-17 register: 0x08 revision id read only rid revision id [7:0] this register speci?s device and revision identi?rs. the value of the LSI53C875e is 0x26 and 0x0 for the LSI53C875. register: 0x09 class code read only cc class code [23:0] this 24-bit register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?s a speci? register level programming interface. the value of this register is 0x010000, which indicates a scsi controller. 7 0 rid LSI53C875e 00100110 LSI53C875 00000100 23 0 cc 000011110000000000000000
3-18 pci functional description register: 0x0c cache line size read/write cls cache line size [7:0] this register speci?s the system cache line size in units of 32-bit words. cache mode is enabled and disabled by the cache line size enable (clse) bit, bit 7 in the dma control (dcntl) register. setting this bit causes the LSI53C875 to align to cache line boundaries before allowing any bursting, except during memory moves in which the read and write addresses are not aligned to a burst size boundary. for more information on this regis- ter, see the section section 3.2.1, ?upport for pci cache line size register. register: 0x0d latency timer read/write lt latency timer [7:0] the latency timer register speci?s, in units of pci bus clocks, the value of the latency timer for this pci bus master. the LSI53C875 supports this timer. all eight bits are writable, allowing latency values of 0?55 pci clocks. use the following equation to calculate an optimum latency value for the LSI53C875: latency = 2 + (burst size x (typical wait states +1)) values greater than optimum are also acceptable. 7 0 cls 00000000 7 0 lt 00000000
con?uration registers 3-19 register: 0x0e header type read only ht header type [7:0] this register identi?s the layout of bytes 0x10 through 0x3f in con?uration space and also whether or not the device contains multiple functions. the value of this register is 0x00. register: 0x10 base address zero (i/o) read/write bar0 base address register zero (i/o) [31:0] this 32-bit register has bit zero hardwired to one. bit 1 is reserved and must return a zero on all reads, and the other bits are used to map the device into i/o space. register: 0x14 base address one (memory) read/write bar1 base address register one [31:0] this register has bit 0 hardwired to zero. for detailed information on the operation of this register, refer to the pci speci?ation. 7 0 ht 00000000 31 0 bar0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 31 0 bar1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0
3-20 pci functional description register: 0x18 ram base address two (memory) scripts ram read/write bar2 base address register two [31:0] this register holds the memory base address of the 4 kbyte internal ram. read this register through the scratch register b (scratchb) register in the operating register set when bit 3 of the chip test two (ctest2) register is set. register: 0x2c subsystem vendor id (ssvid) read only ssvid subsystem vendor id [15:0] this register supports subsystem identi?ation, which has a default value of 0x0000 in the LSI53C875 and 0x1000 in the LSI53C875e (see section 4.1, ?ad bus program- ming ). to write to this register, connect a 4.7 k ? resistor between the mad[6] pin and v ss and leave the mad[4] pin unconnected. the mad[6] and mad[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. in revisions before revision g of the LSI53C875, the mad[6] and mad[4] pins do not support the ssid and ssvid con?urations, and only values of 0x0000 can be found in the subsystem data register. 31 0 bar2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 15 0 ssvid LSI53C875e 1111000000000000 LSI53C875 0000000000000000
con?uration registers 3-21 register: 0x2e subsystem id (ssid) read only ssid subsystem id [15:0] this register supports subsystem identi?ation, which has a default value of 0x0000 in the LSI53C875 and 0x1000 in the LSI53C875e (see section 4.1, ?ad bus program- ming ). to write to this register, connect a 4.7 k ? resistor between the mad[6] pin and v ss and leave the mad[4] pin unconnected. the mad[6] and mad[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. in revisions before revision g of the LSI53C875, the mad[6] and mad[4] pins do not support the ssid and ssvid con?urations, and only values of 0x0000 can be found in the subsystem data register. register: 0x30 expansion rom base address read/write erba expansion rom base address [31:0] this four-byte register handles the base address and size information for expansion rom. it functions exactly like the base address zero (i/o) and base address one (memory) registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. 15 0 ssid LSI53C875e 1111000000000000 LSI53C875 0000000000000000 31 0 erba 00000000000000000000000000000000
3-22 pci functional description the expansion rom enable bit, bit 0, is the only bit de?ed in this register. this bit is used to control whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device can be used with or without an expansion rom depending on the system con?uration. to access the external memory interface, also set the memory space bit in the command register. the host system detects the size of the external memory by ?st writing the expansion rom base address register with all ones and then reading back the register. the LSI53C875 responds with zeros in all don? care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. register: 0x34 capabilities pointer read only cp capabilities pointer [7:0] this register provides an offset into the functions pci con?uration space for the location of the ?st item in the capabilities linked list. only the LSI53C875e sets this register to 0x40. the capability pointer replaces the general purpose pin control (gpcntl) register in earlier revisions of the LSI53C875. 7 0 cp 01000000
con?uration registers 3-23 register: 0x3c interrupt line read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software writes the routing information into this register as it con?ures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin is connected to. values in this register are speci?d by system architecture. register: 0x3d interrupt pin read only ip interrupt pin [7:0] this register tells which interrupt pin the device uses. its value is set to 0x01, for the inta/ signal. 7 0 il 00000000 7 0 ip 00000001
3-24 pci functional description register: 0x3e min_gnt read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value speci?d in these registers is in units of 0.25 microseconds. the LSI53C875 sets this register to 0x11. register: 0x3f max_lat read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. the value speci?d in this register is in units of 0.25 microseconds. values of zero indicate that the device has no major requirements for the settings of latency timers. the LSI53C875 sets this register to 0x40. 7 0 mg 00010001 7 0 ml 01000000
con?uration registers 3-25 register: 0x40 capability id read only cid cap_id [7:0] this register indicates the type of data structure currently being used. it is set to 0x01, indicating the power management data structure. only the LSI53C875e sets this register to 0x01. register: 0x41 next item pointer read only nip next_item_ptr [7:0] bits [7:0] contain the offset location of the next item in the controller capabilities list. the default value for this register is 0x00, indicating that power management is the last capability in the linked list of extended capabilities. this register applies to the LSI53C875e only. register: 0x42 power management capabilities read only this register applies to the LSI53C875e only and indicates the power management capabilities. 7 0 cid 00000001 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes[4:0] d2s d1s r dsi aps pmec ver[2:0] 0 000 0 0 0 0 0 000 0 111
3-26 pci functional description pmes pme support [15:11] this ?ld is always set to 00000b because the LSI53C875e does not provide a pme signal. d2s d2 support 10 this device does not support the d2 power management state, and this bit is set to zero. d1s d1 support 9 this device does not support the d1 power management state, and this bit is set to zero. r reserved [8:6] dsi device speci? initialization 5 this bit is set to 0 to indicate that the device requires no special initialization before the generic class device driver is able to use it. aps auxiliary power source 4 because the device does not provide a pme signal, this bit always returns a 0. this indicates that no auxiliary power source is required to support the pme signal in the d3cold power management state. pmec pme clock 3 this bit always returns a zero value because the devices do not provide a pme signal. ver version [2:0] this ?ld is set to 001b to indicate that the device complies with revision 1.0 of the pci power management interface speci?ation. register: 0x44 power management control/status read/write this register applies to the LSI53C875e only and indicates the power management control and status descriptions. 15 14 13 12 9 8 7 2 1 0 pst dscl dslt pen r pws 00000000 0 0 0 0 0 000
con?uration registers 3-27 pst pme status 15 the device always returns a zero for this bit, indicating that pme signal generation is not supported from d3cold. dscl data scale [14:13] this device does not support the data register. therefore, this ?ld is always set to 00b. dslt data select [12:9] this device does not support the data register. therefore, this ?ld is always set to 0000b. pen pme enable 8 this device always returns a zero for this bit to indicate that pme assertion is disabled. r reserved [7:2] pws power state [1:0] this two bit ?ld determines the current power state for the function and is used to set the function to a new power state. the de?ition of the ?ld values are: register: 0x46 bridge support extensions (pmcsr_bse) read only bse bridge support extensions [7:0] this register applies to the LSI53C875e only and can support pci bridge speci? functionality, if required. the default value always returns 0x00. 0b00 d0 0b01 reserved 0b10 reserved 0b11 d3 hot 7 0 bse 00000000
3-28 pci functional description register: 0x47 data read only data data [7:0] this register applies to the LSI53C875e only and provides an optional mechanism for the function to report state dependent operating data. the LSI53C875e returns 0x00 as the default value. 7 0 data 00000000
LSI53C875/875e pci to ultra scsi i/o processor 4-1 chapter 4 signal descriptions this chapter presents the LSI53C875 pin con?uration and signal de?itions using tables and illustrations. figure 4.1 through figure 4.4 are the pin diagrams for all versions of the LSI53C875 and figure 4.5 is the functional signal grouping. the pin de?itions are presented in table 4.1 through table 4.12 . the LSI53C875 is a pin-for-pin replacement for the lsi53c825.
4-2 signal descriptions figure 4.1 LSI53C875 pin diagram c_be3/ ad23 ad22 v dd-i ad18 c_be2/ irdy/ v ss stop/ par/ v ss ad15 ad11 v ss ad8 c_be0/ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 ad17 v ss v ss v dd-i 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 idsel v ss ad20 v ss ad16 frame/ v dd-i v ss c_be1/ ad13 ad12 ad9 ad21 ad19 trdy/ devsel/ perr/ ad14 ad10 ad7 sdir7 v dd sd13/ sd15/ sd1/ sd4/ v ss-s sd6/ v ss-s srst/ ssel/ v ss-s sd9/ v dd sdir8 sdir9 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 85 84 83 82 81 v ss-s sd3/ si_o/ v ss-s 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 sdirp0 sd12/ v ss-s sd0/ sd2/ sd5/ satn/ sbsy/ smsg/ sreq/ sd8/ sd11/ sd14/ sdp1/ sd7/ sdp0/ sack/ sc_d/ sd10/ sdir10 ad6 ad5 v dd-i v ss v dd-c v ss-c testin mac/_testout mad4 mad2 mad0 gpio2_mas2/ v dd rstdir bsydir v ss irq/ gpio1_master/ gpio4 tgs v ss ad4 ad2 ad0 gpio0_fetch/ sclk mad5 v dd mad1 gpio3 diffsens seldir ad3 ad1 mad7 mad6 mad3 v ss igs v ss sdir3 sdir2 sdirp1 v ss sdir12 mas1/ big_lit/ clk v ss-c gnt/ v dd-c ad31 ad30 ad28 121 123 125 127 129 131 133 135 137 139 141 143 144 145 146 147 148 150 152 154 156 158 sdir5 mwe/ mce/ v ss ad29 ad27 ad26 ad24 160 ad25 122 124 126 128 130 132 134 136 138 140 142 149 151 153 155 157 159 sdir6 sdir4 sdir0 sdir15 sdir13 v dd moe/ rst/ sdir1 v dd sdir14 mas0/ serr/ req/ v dd-i v ss 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 76 77 78 79 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 sdir11 note: the decoupling capacitor arrangement shown above is recommended to maximize the bene?s of the internal split ground system. capacitor values between 0.01 and 0.1 f should provide adequate noise isolation. because of the number of high current drivers on the LSI53C875, a multilayer pc board with power and ground planes is required. LSI53C875 pci to scsi i/o processor 160-pin quad flat pack (top view)
4-3 figure 4.2 LSI53C875j pin diagram c_be3/ ad23 ad22 v dd-i ad18 c_be2/ irdy/ v ss stop/ par/ v ss ad15 ad11 v ss ad8 c_be0/ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 ad17 v ss v ss v dd-i 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 idsel v ss ad20 v ss ad16 frame/ v dd-i v ss c_be1/ ad13 ad12 ad9 ad21 ad19 trdy/ devsel/ perr/ ad14 ad10 ad7 sdir7 v dd sd13/ sd15/ sd1/ sd4/ v ss-s sd6/ v ss-s srst/ ssel/ v ss-s sd9/ v dd sdir8 sdir9 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 85 84 83 82 81 v ss-s sd3/ si_o/ v ss-s 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 sdirp0 sd12/ v ss-s sd0/ sd2/ sd5/ satn/ sbsy/ smsg/ sreq/ sd8/ sd11/ sd14/ sdp1/ sd7/ sdp0/ sack/ sc_d/ sd10/ sdir10 ad6 ad5 v dd-i v ss v dd-c v ss-c tms tdo mad4 mad2 mad0 gpio2_mas2/ v dd rstdir bsydir v ss irq/ gpio1_master/ gpio4 tgs v ss ad4 ad2 ad0 gpio0_fetch/ sclk mad5 v dd mad1 gpio3 diffsens seldir ad3 ad1 mad7 mad6 mad3 v ss igs v ss sdir3 sdir2 tck v ss sdir12 mas1/ tdi clk v ss-c gnt/ v dd-c ad31 ad30 ad28 121 123 125 127 129 131 133 135 137 139 141 143 144 145 146 147 148 150 152 154 156 158 sdir5 mwe/ mce/ v ss ad29 ad27 ad26 ad24 160 ad25 122 124 126 128 130 132 134 136 138 140 142 149 151 153 155 157 159 sdir6 sdir4 sdir0 sdir15 sdir13 v dd moe/ rst/ sdir1 v dd sdir14 mas0/ serr/ req/ v dd-i v ss 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 76 77 78 79 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 sdir11 LSI53C875j (jtag) pci to scsi i/o processor 160-pin quad flat pack (top view) note: the decoupling capacitor arrangement shown above is recommended to maximize the bene?s of the internal split ground system. capacitor values between 0.01 and 0.1 f should provide adequate noise isolation. because of the number of high current drivers on the LSI53C875, a multilayer pc board with power and ground planes is required.
4-4 signal descriptions figure 4.3 LSI53C875n pin diagram nc nc nc bytepar2 ad22 ad19 ad18 ad17 frame/ trdy/ v dd-i stop/ bytepar1 ad13 v ss ad12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 ad21 v dd-i pa r v ss 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 nc nc idsel v ss ad20 v ss c_be2/ irdy/ devsel/ perr/ c_be1/ ad14 c_be3/ ad23 ad16 v ss v ss v ss ad15 v dd-i nc nc nc sdirp0 sd13 sdp1/ sd1/ v ss-s sd5/ sd7/ satn/ v ss-s v ss-s si_0/ sd8/ v ss-s 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 121 120 119 118 117 sd14/ sd15/ srst/ ssel/ 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 nc nc sdir7 sd12/ v ss-s sd0/ sd4/ v ss-s sdp0/ sack/ smsg/ sreq/ nc v dd sd2/ sd3/ sd6/ sbsy/ sc_d/ sd9/ nc nc nc ad5 ad3 ad0 irq/ gpio0_fetch testin td0 mad6 mad5 mad0 gpio3 gpio4 diffsens ad2 ad1 mad3 mad1 nc nc v ss v dd-i v ss v dd-c sclk tms mad7 v dd mad2 v ss ad6 ad4 gpio1_master/ v ss-c mac/_testout mad4 gpio2_mas2/ sdirp1 sdir15 sdir14 mas1 mwe/ mce/ big_lit/ gnt/ bytepar3 ad31 ad30 ad29 ad28 v dd-i v ss 169 171 173 175 177 179 181 183 185 187 189 191 192 193 194 195 196 198 200 202 204 206 sdir0 rst/ v ss-c ad27 ad26 ad24 nc nc 208 nc 170 172 174 176 178 180 182 184 186 188 190 197 199 201 203 205 207 v dd tck sdir12 mas0/ moe/ serr/ clk v dd-c v ss sdir13 v dd tdi req/ v ss ad25 nc 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 88 89 90 91 92 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 LSI53C875n pci to scsi i/o processor 208-pin quad flat pack 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 121 120 119 118 117 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 116 114 112 110 108 106 115 113 111 109 107 105 sd10/ v dd sdir9 nc nc nc sd11/ sdir8 nc nc sdir10 nc 41 43 45 47 48 49 50 51 52 42 44 46 c_be0/ nc nc nc ad9 ad8 ad10 v ss ad7 ad11 bytepar0 nc 93 95 97 99 100 101 102 103 104 94 96 98 tgs v dd sdir11 nc nc nc rstdir v ss seldir bsydir nc igs nc nc nc sdir6 sdir3 157 159 161 163 165 167 nc 158 160 162 164 166 168 nc nc sdir4 sdir2 sdir5 v ss sdir1 note: the decoupling capacitor arrangement shown in figures 4.1 and 4.2 is recom- mended to maximize the bene?s of the internal split ground system. capacitor val- ues between 0.01 and 0.1 f should provide adequate noise isolation. because of the number of high current drivers on the LSI53C875, a multilayer pc board with power and ground planes is required.
4-5 figure 4.4 LSI53C875jb pin diagram (top view) note: pins f7, g6, g7, g8, and h7 are connected to the die pad. a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 c_be3/ ad24 ad27 ad29 vdd-c clk mce/ mas0/ vss tck sdir2 sdir5 sdir6 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 idsel nc vss ad28 ad31 rst/ mde/ mas1/ sdir14 vdd vss nc sdir7 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 ad21 ad23 vss ad26 ad30 vss-c mwe/ sdir12 sdir15 sdir1 sdir4 vdd-s sd13/ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 vss vdd-1 ad20 ad25 vdd-1 gnt/ tdi sdir13 sdir0 sdirp0 sd12 vss-s sd15/ e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 ad16 ad17 ad18 ad19 ad22 req/ serr/ vdd sdir3 sd14/ sd0/ sd1/ vss-s f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 irdy/ frame/ c_be2/ vss vss vss nc sdp1/ sd2/ sd3/ sd4/ vss-s sd5/ g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 vdd devsel/ trdy/ stop/ vss nc nc nc sd6/ sd7/ vss-s satn/ sdp0/ h1 h2 h3 h4 h5 h5 h7 h8 h9 h10 h11 h12 h13 par perr/ c-be1/ vss ad15 ad12 nc diffsens sbsy/ ssel/ smsg/ srst/ sack/ j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 ad14 ad13 vss ad10 vdd-1 td0 vdd gpio_ mas2/ sd11/ sd8/ sreq/ sc_d/ vss-s k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 vdd-1 ad11 vss c_be0/ ad1 gpio1_ master/ mad4 mad0 igs vss sd9/ vss-s si_0/ l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 ad9 ad8 ad4 ad2 vdd-c vss-c mad7 mad1 gpio4 rstdir vdd-s sdir8 sd10/ m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 ad7 nc ad5 vss irq/ sclk mad6 mad3 gpio3 vdd bsydir nc sdir9 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 ad6 vss ad3 ad0 gpio_ fetch/ tms mad5 mad2 vss tgs seldir sdir11 sdir10
4-6 signal descriptions the pci/scsi pin de?itions are organized into the following functional groups: system, address/data, interface control, arbitration, error reporting, scsi, and optional interface. a slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage. there are four signal type de?itions: i input, a standard input-only signal. o output, a standard output driver (typically a totem pole output). t/s 3-state, a bidirectional, 3-state input/output signal. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time.
4-7 table 4.1 describes the LSI53C875, LSI53C875j, LSI53C875e, and LSI53C875je power and ground signals group. table 4.2 describes the LSI53C875n power and ground signals group. table 4.1 LSI53C875, LSI53C875j, LSI53C875e, and LSI53C875je power and ground signals name pin no. description v ss 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 123, 133, 152, 158 ground to the pci i/o pins. v dd 63, 74, 84, 118, 128, 138 power supplies to the standard i/o pins. v dd-i 1 1. these pins can accept a v dd source of 3.3 v or 5 v. all other v dd pins must be supplied 5 v. 8, 21, 33, 45, 155 v dd pad for pci i/o pins. v ss -s 88, 93, 99, 104, 109, 114 ground to the scsi bus i/o pins. v ss -c 55, 146 ground to the internal logic core. v dd -c 51, 149 power supplies to the internal logic core. table 4.2 LSI53C875n power and ground signals name pin no. description v ss 10, 16, 20, 24, 29, 33, 38, 44, 59, 65, 88, 98, 164, 175, 196, 202 ground to the pci i/o pins. v dd 82, 93, 148, 169, 180 power supplies to the standard i/o pins. v dd-i 1 1. these pins can accept a v dd source of 3.3 v or 5 v. all other v dd pins must be supplied 5 v. 14, 27, 62, 199 v dd pad for pci i/o pins. v ss -s 118, 123, 129, 134, 139, 144 ground to the scsi bus i/o pins. v ss -c 72, 189 ground to the internal logic core. v dd -c 68, 192 power supplies to the internal logic core.
4-8 signal descriptions table 4.3 describes the LSI53C875jb and LSI53C875jbe power and ground signals group. table 4.3 LSI53C875jb and LSI53C875jbe power and ground signals name pin no. description v ss a9, b3, b11, c3, d1, f4, f5, f6, g5, h4, j3, k3, k10, m4, n2, n9 ground to the pci i/o pins. v dd b10, e8, j7, m10 power supplies to the standard i/o pins. v dd-i 1 1. these pins can accept a v dd source of 3.3 v or 5 v. all other v dd pins must be supplied 5 v. d2, d5, g1, j5, k1 v dd pad for pci i/o pins. v dd -s c12, l11 ground to the scsi bus i/o pins. v ss -c l6, c6 ground to the internal logic core. v dd -c a5, l5 power supplies to the internal logic core.
4-9 figure 4.5 is the functional signal grouping for the LSI53C875. figure 4.5 LSI53C875 functional signal grouping LSI53C875 clk rst ad[31:0] c_be[3:0]/ pa r frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ serr/ perr/ tgs gpio3 gpio0_fetch/ gpio1_master/ mac/_testout irq/ big_lit/ diffsens gpio2_mas2/ mwe/ mce/ moe/ mas0/ system address and data interface control arbitration error reporting scsi mas1/ bsydir rstdir seldir igs sdirp[1:0] sdir[15:0] sclk sd[15:0] sdp[1:0] sctrl additional interface mad[7:0] testin/ external memory interface memory
4-10 signal descriptions table 4.4 describes the system signals group. table 4.4 system signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb typ e description clk 145/188/a6 i clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are de?ed with respect to this edge. clock can optionally serve as the scsi core clock, but this may effect the fast scsi transfer rates. rst/ 144/187/b6 i reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device.
4-11 table 4.5 describes the address and data signals group. table 4.5 address and data signals name pin no. typ e description ad[31:0] LSI53C875 LSI53C875j: 150, 151, 153, 154, 156, 157, 159, 160, 3, 5, 6, 7, 9, 11, 12, 13, 28, 29, 30, 32, 34, 35, 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 LSI53C875n: 194, 195, 197, 198, 200, 201, 203, 204, 9, 11, 12, 13, 15, 17, 18, 19, 35, 36, 37, 39, 41, 42, 43, 45, 48, 58, 60, 61, 63, 64, 66, 67 LSI53C875jb: b5, c5, a4, b4, a3, c4, d4, a2, c2, e5, c1, d3, e4, e3, e2, e1, h5, j1, j2, h6, k2, j4, l1, l2, m1, n1, m3, l3, n3, l4, k5, n4 t/s physical longword address and data are multiplexed on the same pci pins. during the ?st clock of a transaction, ad[31:0] contain a physical address. during subsequent clocks, ad[31:0] contain data. a bus transaction consists of an address phase, followed by one or more data phases. pci supports both read and write bursts. ad[7:0] de?e the least signi?ant byte, and ad[31:24] de?e the most signi?ant byte. c_be[3:0]/ LSI53C875 LSI53C875j: 1, 15, 26, 39 LSI53C875n: 6, 21, 32, 46 LSI53C875jb: a1,f3, h3, k4 t/s bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ de?e the bus command. during the data phase, c_be[3:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be[0]/ applies to byte 0, and c_be[3]/ to byte 3.
4-12 signal descriptions table 4.6 describes the interface control signals group. par LSI53C875, LSI53C875j: 25 LSI53C875n: 31 LSI53C875jb: h1 t/s parity is the even parity bit that protects the ad[31:0] and c_be[3:0]/ lines. during address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered. bytepar[3:0] (LSI53C875n only) 193, 8, 34, 47 t/s when the pci byte parity pins are enabled, the LSI53C875n checks each byte of incoming data on the pci bus against its corresponding parity line, in addition to the normal parity checking against the pci par signal. this extra parity checking/generation is always enabled for the LSI53C875n. is not register selectable. a parity error on any byte parity pin for pci master read or slave write operation causes a fatal dma interrupt and scripts stops running. mask this interrupt with the extended byte parity enable bit, bit 1 of the dma interrupt enable (dien) register. table 4.5 address and data signals (cont.) name pin no. typ e description table 4.6 interface control signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description frame/ 16/22/f2 s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate a bus transaction is beginning. while frame/ is asserted, data transfers continue. when frame/ is deasserted, the transaction is in the ?al data phase or the bus is idle. trdy/ 19/25/g3 s/t/s target ready indicates the target agents (selected devices) ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together.
4-13 table 4.7 describes the arbitration signals group. irdy/ 17/23/f1 s/t/s initiator ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. irdy/ is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates that the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 22/28/g4 s/t/s stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 20/26/g2 s/t/s device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 2/7/b1 i initialization device select is used as a chip select in place of the upper 24 address lines during con?uration read and write transactions. table 4.6 interface control signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description table 4.7 arbitration signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb typ e description req/ 148/191/e6 o request indicates to the system arbiter that this agent desires use of the pci bus. this is a point-to-point signal. every master has its own req/ signal. gnt/ 147/190/d6 i grant indicates to the agent that access to the pci bus has been granted. this is a point-to-point signal. every master has its own gnt/ signal.
4-14 signal descriptions table 4.8 describes the error reporting signals group. table 4.8 error reporting signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description perr/ 24/30/h2 s/t/s parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruptions. serr/ 143/186/e7 o system error is an open drain output used to report address parity errors. on detection of a perr/ pulse, the central resource generates a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing completes.
4-15 table 4.9 describes the scsi signals group. table 4.9 scsi signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description sclk 56/73/m6 i scsi clock is used to derive all scsi-related timings. the speed of this clock is determined by the applications requirements. in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd[15:0]/, sdp[1:0]/ LSI53C875, LSI53C875j: 113, 115, 116, 117, 85, 86, 87, 89, 102, 103, 105, 106, 107, 108, 110, 111, 112, 101 LSI53C875n: 143, 145, 146, 147, 115, 116, 117, 119, 132, 133, 135, 136, 137, 138, 140, 141, 142, 131 LSI53C875jb: d13, e10, c13, d11, j9, l13 k11, j10, g10, g9, f13, f11, f10, f9, e12, e11, f8, g13 i/o scsi data includes the following data lines and parity signals: sd[15:0]/ (16-bit scsi data bus), and sdp[1:0]/ (scsi data parity bits).
4-16 signal descriptions sctrl/ LSI53C875, LSI53C875j: 92, 90, 95, 91, 97, 98, 100, 96, 94 LSI53C875n: 122, 120, 125, 121, 127, 128, 130, 126, 124 LSI53C875jb: j12, k13, h11, j11, h13, h9, g12, h12, h10 i/o scsi control includes the following signals: sc_d/ scsi phase line, command/data si_o/ scsi phase line, input/output smsg/ scsi phase line, message sreq/ data handshake signal from target device sack/ data handshake signal from initiator device sbsy/ scsi bus arbitration signal, busy satn/ scsi attention, the initiator is requesting a message out phase srst/ scsi bus reset ssel/ scsi bus arbitration signal, select device sdir[15:0] LSI53C875, LSI53C875j: 131, 132, 134, 135, 80, 81, 82, 83, 120, 121, 122, 124, 125, 126, 127, 129 LSI53C875n: 173, 174, 176, 177, 99, 111, 112, 113, 150, 162, 163, 165, 166, 167, 168, 170 LSI53C875jb: c9, b9, d8, c8, n12, n13, m13, l12, b13, a13, a12, c11, e9, a11, c10, d9 o driver direction control for scsi data lines. table 4.9 scsi signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description
4-17 sdirp[1:0] (sdipr1 is not available on LSI53C875j, LSI53C875jb) 130, 119; na, 119/171, 149/na, d10 o driver direction control for scsi parity signals. in the LSI53C875j and LSI53C875jb, this pin is replaced by the tck jtag signal. if the device is used in a wide differential system, use the sdirp0 pin to control the direction of the differential transceiver for both the sp0 and sp1 signals. the sdirp0 signal is capable of driving both direction inputs from a transceiver. seldir 76/95/n11 o driver enable control for scsi sel/ signal. rstdir 77/96/l10 o driver enable control for scsi rst/ signal. bsydir 78/97/m11 o driver enable control for scsi bsy/ signal. igs 75/94/k9 o direction control for initiator driver group. tgs 73/92/n10 o direction control for target driver group. table 4.9 scsi signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description
4-18 signal descriptions table 4.10 describes the additional interface signals group. table 4.10 additional interface signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description testin (not available on LSI53C875j, LSI53C875jb) 57, na/74/na i test in . when this pin is driven low, the LSI53C875 connects all inputs and outputs to an ?nd tree. the scsi control signals and data lines are not connected to the ?nd tree. the output of the ?nd tree is connected to the test out pin. this allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached. when the testin pin is driven low, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals will be 3-stated, and the mac/_testout pin will be enabled. connectivity can be tested by driving one of the LSI53C875 pins low. the mac/_testout pin should respond by also driving low. gpio0_ fetch/ 53/70/n5 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the next bus request will be for an opcode fetch. this pin powers up as a general purpose input. this pin has two speci? purposes in the lsi logic sdms software. sdms software uses it to toggle scsi device leds, turning on the led whenever the LSI53C875 is on the scsi bus. sdms software drives this pin low to turn on the led, or drives it high to turn off the led. this signal can also be used as data i/o for serial eeprom access. in this case it is used with the gpio0 pin, which serves as a clock, and the pin can be controlled from pci con?uration register 0x35 or observed from the general purpose (gpreg) operating register, at address 0x07. gpio1_ master/ 54/71/k6 i/o general purpose i/o pin. optionally, when driven low, indicates that the LSI53C875 is bus master. this pin powers up as a general purpose input. lsi logic sdms software supports use of this signal in serial eeprom applications, when enabled, in combination with the gpio0 pin. when this signal is used as a clock for serial eeprom access, the gpio1 pin serves as data, and the pin is controlled from pci con?uration register 0x35.
4-19 gpio[4:3] 71, 70/90, 89/l9, m9 i/o general purpose i/o pins. gpio4 powers up as an output. it can be used as the enable line for v pp , the 12 v power supply to the external flash memory interface. gpio3 powers up as an input. lsi logic sdms software uses gpio3 to detect a differential board. if the pin is pulled low externally, the board is con?ured by sdms software as a differential board. if it is pulled high or left ?ating, sdms software con?ures it as an se board. the lsi logic pci to scsi host adapters use the gpio4 pin in the process of ?shing a new sdms software rom. diffsens 72/91/h8 i the differential sense pin detects the presence of an se device on a differential system. when external differential transceivers are used and a zero is detected on this pin, all chip scsi outputs will be 3-stated to avoid damage to the transceivers. this pin should be tied high during se operation. the normal value of this pin is 1. mac/_ testout (not available on LSI53C875, LSI53C875jb) 58, na/76/na t/s memory access control . this pin can be programmed to indicate local or system memory accesses (non-pci applications). it is also used to test the connectivity of the LSI53C875 signals using an ?nd tree scheme. the mac/_testout pin is only driven as the test out function when the testin/ pin is driven low. irq/ 52/69/m5 o interrupt . this signal, when asserted low, indicates that an interrupting condition has occurred and that service is required from the host cpu. the output drive of this pin is programmed as either open drain with an internal weak pull-up or, optionally, as a totem pole driver. refer to the description of dma control (dcntl) register, bit 3, for additional information. table 4.10 additional interface signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description
4-20 signal descriptions big_lit/ (not available on LSI53C875j, LSI53C875jb) 142, na/184/na i big_little endian select . when this pin is driven low, the LSI53C875 routes the ?st byte of an aligned scsi to pci transfer to byte lane zero of the pci bus and subsequent bytes received are routed to ascending lanes. an aligned pci to scsi transfer routes pci byte lane zero onto the scsi bus ?st, and transfers ascending byte lanes in order. when this pin is driven high, the LSI53C875 routes the ?st byte of an aligned scsi-to-pci transfer to byte lane three of the pci bus and subsequent bytes received are routed to descending lanes. an aligned pci-to-scsi transfer routes pci byte lane three onto the scsi bus ?st and transfers descending byte lanes in order. this mode of operation also applies to the external memory interface. when this pin is driven in little endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane zero and the data accessed at location 0x00003 is routed to pci byte lane three. when the chip is performing a write to flash memory, pci byte lane zero is routed to location 0x00000 and ascending byte lanes are routed to subsequent memory locations. when this pin is driven in big endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane three and the data accessed at location 0x00003 is routed to byte lane zero. when the chip is performing a write to flash memory, pci byte lane three is routed to location 0x00000 and descending byte lanes are routed to subsequent memory locations. table 4.10 additional interface signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb type description
4-21 table 4.11 describes the external memory interface signals group. table 4.11 external memory interface signals name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb typ e description mas0/ 137/179/a8 o memory address strobe 0 . this pin is used to latch in the least signi?ant address byte of an external eprom or flash memory. since the LSI53C875 moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?p-?ps which are used to assemble up to a 20-bit address for the external memory. mas1/ 136/178/b8 o memory address strobe 1 . this pin is used to latch in the address byte corresponding to address bits [15:8] of an external eprom or flash memory. since the LSI53C875a moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?p-?ps which assemble up to a 20-bit address for the external memory. mad[7:0] LSI53C875, LSI53C875e, LSI53C875j, LSI53C875je: 59, 60, 61, 62, 64, 65, 66, 67 59, 60, 61, 62, 64, 65, 66, 67 LSI53C875n: 78, 79, 80, 81, 83, 84, 85, 86 LSI53C875jb, LSI53C875jb e: l7, m7, n7, k7, m8, n8, l8, k8 i/o memory address/data bus . this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eprom or flash memory. this bus will put out the most signi?ant byte ?st and ?ish with the least signi?ant bits. it is also used to write data to a flash memory or read data into the chip from external eprom/flash memory. see section 4.1, ?ad bus programming, for more details. mwe/ 139/181/c7 o memory write enable . this pin is used as a write enable signal to an external flash memory. moe/ 140/182/b7 o memory output enable . this pin is used as an output enable signal to an external eprom or flash memory during read operations. mce/ 141/183/a7 o memory chip enable . this pin is used as a chip enable signal to an external eprom or flash memory device.
4-22 signal descriptions table 4.12 describes the jtag signals group for the LSI53C875j, LSI53C875n, and LSI53C875jb. 4.1 mad bus programming the mad[7:0] pins, in addition to serving as the address/data bus for the local memory interface, are also used to program power-up options for the chip. a particular option is programmed by connecting a 4.7 k ? resistor between the appropriate mad[x] pin and vss. the pull-down resistors require that hc or hct external components are used for the memory interface. ? mad[7] has no functionality. do not place a pull-down resistor on this pin. gpio2_ mas2/ 68 /87/j8 i/o general purpose i/o pin. optionally, this pin is used as a memory address strobe 2 if an external memory with more than 16 bits of addressing is speci?d by the pull-down resistors at power-up and bit 0 in the expansion rom base address register is set. table 4.11 external memory interface signals (cont.) name pin no. LSI53C875, LSI53C875j, LSI53C875n, LSI53C875jb typ e description table 4.12 jtag signals (LSI53C875j/LSI53C875n/LSI53C875jb only) name pin no. LSI53C875j, LSI53C875n, LSI53C875jb type description tck 130/172/a10 test clock pin for jtag boundary scan. tms 57/75/n6 test mode select pin for jtag boundary scan. tdi 142/185/d7 test data in pin for jtag boundary scan. tdo 58/77/j6 test data out pin for jtag boundary scan.
mad bus programming 4-23 ? mad[6] subsystem data con?uration. refer to table 4.13 and table 4.14 for the different con?urations. ? mad[5] scripts ram disable. connecting a 4.7 k ? resistor between mad[5] and vss disables scripts ram. ? mad[4] subsystem data con?uration. refer to table 4.13 and table 4.14 for the different con?urations. note: the chip revisions before revision g of the LSI53C875 (pci rev id 0x04) do not support different subsystem data con?urations. the subsystem id (ssid) and subsystem vendor id (ssvid) registers are hard wired to zero values. ? mad[3:1] used to set the size of the external expansion rom device attached. encoding for these pins are listed in table 4.15 . table 4.13 subsystem data con?uration table for the LSI53C875e (pci rev id 0x26) mode mad pins offset normal 4-hi, 6-hi read/write 4-hi, 6-lo reserved 4-low, 6-hi lsi logic 4-low, 6-lo vendor id 0x00 0x1000 0x1000 0x1000 device id 0x02 0x000f 0x000f 0x000f subsystem vendor id 0x2c 0x1000 0x0000 0x0000 subsystem id 0x2e 0x1000 0x0000 0x0000 table 4.14 subsystem data con?uration table for the LSI53C875 (pci rev id 0x04), revision g only mode mad pins offset normal 4-hi, 6-hi read/write 4-hi, 6-lo reserved 4-low, 6-hi lsi logic 4-low, 6-lo vendor id 0x00 0x1000 0x1000 0x1000 device id 0x02 0x000f 0x000f 0x000f subsystem vendor id 0x2c 0x1000 0x0000 0x0000 subsystem id 0x2e 0x1000 0x0000 0x0000
4-24 signal descriptions ? mad[0] slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. note: all mad pins have internal pull-up resistors. table 4.15 external memory support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
LSI53C875/875e pci to ultra scsi i/o processor 5-1 chapter 5 scsi operating registers this section contains descriptions of all LSI53C875 operating registers. table 5.1 lists registers by operating and con?uration addresses. the terms ?et and ?ssert are used to refer to bits that are programmed to a binary one. similarly, the terms ?eassert, ?lear, and ?eset are used to refer to bits that are programmed to a binary zero. any bits marked as reserved should always be written to zero; mask all information read from them. reserved bit functions may be changed at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. note: the only register that the host cpu can access while the LSI53C875 is executing scripts is the interrupt status (istat) register. attempts to access other registers interferes with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. the LSI53C875 cannot fetch scripts instructions from the operating register space. instructions must be fetched from system memory or the internal scripts ram.
5-2 scsi operating registers . table 5.1 LSI53C875 register map 31 16 15 0 mem i/o con? scntl3 scntl2 scntl1 scntl0 0x00 0x80 gpreg sdid sxfer scid 0x04 0x84 sbcl ssid socl sfbr 0x08 0x88 sstat2 sstat1 sstat0 dstat 0x0c 0x8c dsa 0x10 0x90 reserved istat 0x14 0x94 ctest3 ctest2 ctest1 reserved 0x18 0x98 temp 0x1c 0x9c ctest6 ctest5 ctest4 dfifo 0x20 0xa0 dcmd dbc 0x24 0xa4 dnad 0x28 0xa8 dsp 0x2c 0xac dsps 0x30 0xb0 scratch a 0x34 0xb4 dcntl sbr dien dmode 0x38 0xb8 adder 0x3c 0xbc sist1 sist0 sien1 sien0 0x40 0xc0 gpcntl macntl swide slpar 0x44 0xc4 respid1 respid0 stime1 stime0 0x48 0xc8 stest3 stest2 stest1 stest0 0x4c 0xcc reserved sidl 0x50 0xd0 reserved sodl 0x54 0xd4 reserved sbdl 0x58 0xd8 scratch b 0x5c 0xdc scratch c 0x60 0xe0 scratch d 0x64 0xe4 scratch e 0x68 0xe8 scratch f 0x6c 0xec scratch g 0x70 0xf0 scratch h 0x74 0xf4 scratch i 0x78 0xf8 scratch j 0x7c 0xfc
5-3 register: 0x00 (0x80) scsi control zero (scntl0) read/write arb1[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the LSI53C875 waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the LSI53C875 deasserts sbsy/, deasserts its id, and sets the lost arbitration bit (bit 3) in the scsi status zero (sstat0) register. 3. after an arbitration delay, the cpu should read the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the LSI53C875 wins arbitration. 4. once the LSI53C875 wins arbitration, ssel/ must be asserted using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 s) before a low level selection is performed. full arbitration, selection/reselection 1. the LSI53C875 waits for a bus free condition. 76543210 arb[1:0] start watn epc r aap trg 11000 x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection
5-4 scsi operating registers 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scsi chip id (scid) register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the LSI53C875 detects a higher priority id, the LSI53C875 deasserts bsy, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the LSI53C875 repeats arbitration until it wins control of the scsi bus. when it wins, the won arbitration bit is set in the scsi status zero (sstat0) register, bit 2. 5. the LSI53C875 performs selection by asserting the following onto the scsi bus: ssel/, the targets id (stored in the scsi destination id (sdid) register), and the LSI53C875s id (stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the scsi interrupt status zero (sist0) register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi interrupt status one (sist1) register, bit 2. start start sequence 5 when this bit is set, the LSI53C875 starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. do not start an arbitration sequence if the connected (con) bit in the scsi control one (scntl1) register, bit 4, indicates that the LSI53C875 is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence is aborted, check bit 4 in the scsi control one (scntl1) register to verify that the LSI53C875 is not connected to the scsi bus. watn select with satn/ on a start sequence 4 when this bit is set and the LSI53C875 is in the initiator mode, the satn/ signal is asserted during selection of a scsi target device. this is to inform the target that the LSI53C875 has a message to send. if a selection
5-5 time-out occurs while attempting to select a target device, satn/ is deasserted at the same time ssel/ is deasserted. when this bit is cleared, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but manual setting is possible in low level mode. epc enable parity checking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either initiator or target mode. parity is also checked as data goes from the scsi fifo to the dma fifo. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the LSI53C875 is operating in the initiator mode and a parity error is detected, assertion of satn/ is optional, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. when these bits are set in the LSI53C875n, the chip again checks inbound scsi parity at the scsi fifo dma fifo interface after the data has passed through the scsi fifo. the parity bits are not passed through the dma fifo, but parity is generated before the data is sent out on the pci bus. r reserved 2 aap assert satn/ on parity error 1 when this bit is set, the LSI53C875 automatically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in the initiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. also set the enable parity checking bit for the LSI53C875 to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity error is received.
5-6 scsi operating registers trg target mode 0 this bit determines the default operating mode of the LSI53C875. the user must manually set the target or initiator mode. this is done using the scripts language ( set tartet or clear target ). when this bit is set, the chip is a target device by default. when this bit is cleared, the LSI53C875 is an initiator device by default. note: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes. register: 0x01 (0x81) scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi send data transfer. the extra data setup time can provide additional system design margin, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. adb assert scsi data bus 6 when this bit is set, the LSI53C875 drives the contents of the scsi output data latch (sodl) onto the scsi data bus. when the LSI53C875 is an initiator, the scsi i/o signal must be inactive to assert the scsi output data latch (sodl) contents onto the scsi bus. when the LSI53C875 is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the scsi output data latch (sodl) register can be asserted at any time, even before the LSI53C875 is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostics testing or operation in low level mode. 76543210 exc adb dhp con rst aesp iarb sst 00000000
5-7 dhp disable halt on parity error or atn (target only) 5 the dhp bit is only de?ed for target mode. when this bit is cleared, the LSI53C875 halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is received in the middle of a data transfer, the LSI53C875 may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the LSI53C875 transfers data until there are no outstanding synchronous offsets. if the LSI53C875 is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the LSI53C875 does not halt the scsi transfer when satn/ or a parity error is received. con connected 4 this bit is automatically set any time the LSI53C875 is connected to the scsi bus as an initiator or as a target. it is set after the LSI53C875 successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the LSI53C875 is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature is used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 s minimum assertion time de?ed in the scsi speci?ation must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the LSI53C875 asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the chip. if parity checking is enabled, then the LSI53C875 checks data received for odd parity. this bit is used for diagnostic testing and should be cleared for normal operation. it is useful to generate parity errors to test error handling functions.
5-8 scsi operating registers iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected following an expected scsi disconnect. this bit is useful for multithreaded applications. the arb[1:0] bits in scsi control zero (scntl0) register are set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the LSI53C875 holds bsy and sel asserted, and waits for a select or reselect sequence. the immediate arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out. an unexpected disconnect condition clears iarb without attempting arbitration. see the scsi disconnect unexpected bit ( scsi control two (scntl2) , bit 7) for more information on expected versus unexpected disconnects. during the time between the setting of the iarb bit and the completion of a select/reselect instruction, dma interrupts are disabled. therefore, interrupt instructions that are issued during this time period will not execute. it is possible to abort an immediate arbitration sequence. first, set the abort bit in the interrupt status (istat) register. then one of two things eventually happens: ? the won arbitration bit ( scsi status zero (sstat0), bit 2) will be set. in this case, the immediate arbitration bit needs to be cleared. this completes the abort sequence and disconnects the chip from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, it is possible to perform a low level selection instead. ? the abort completes because the LSI53C875 loses arbitration. this is detected by the clearing of the immediate arbitration bit. do not use the lost arbitration bit ( scsi status zero (sstat0), bit 3) to detect this condition. take no further action in this case. sst start scsi transfer 0 this bit is automatically set during scripts execution and should not be used. it causes the scsi core to begin a scsi transfer, including sreq/sack handshaking.
5-9 the determination of whether the transfer is a send or receive is made according to the value written to the i/o bit in scsi output control latch (socl) . this bit is self-clearing. do not set it for low level operation. note: writing to this register while not connected may cause the loss of a selection/reselection by resetting the connected bit. register: 0x02 (0x82) scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in the initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the scsi interrupt status zero (sist0) register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be cleared with a register write (move 0x00 to scntl2) before the scsi core expects a disconnect to occur, normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode is primarily used to transfer consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behav- ior. when this bit is set and a data transfer ends on an 76543210 sdu chm slpmd slphben wss vue0 vue1 wsr 00000000
5-10 scsi operating registers odd byte boundary, the LSI53C875 stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is combined with the ?st byte from the subsequent transfer so that a wide transfer is completed. for more information, see section 2.5.14, ?hained block moves, in chapter 2, ?unctional description. slpmd slpar mode bit 5 if this bit is cleared, the scsi longitudinal parity (slpar) register functions like the lsi53c825. if this bit is set, the scsi longitudinal parity (slpar) register re?cts the high or low byte of the slpar word, depending on the state of scsi control two (scntl2), bit 4. it also allows a seed value to be written to the scsi longitudinal parity (slpar) register. slphben slpar high byte enable 4 if this bit is cleared, the low byte of the slpar word is present in the scsi longitudinal parity (slpar) register. if this bit is set, the high byte of the slpar word is present in the scsi longitudinal parity (slpar) register. wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) ?g. asserting this bit clears the wss ?g. this clearing function is self-clearing. when the wss ?g is high following a wide scsi send operation, the scsi core is holding a byte of ?hain data in the scsi output data latch (sodl) register. this data becomes the ?st low-order byte sent when married with a high-order byte during a subsequent data send transfer. performing a scsi receive operation clears this bit. also, performing any nonwide transfer clears this bit. vue0 vendor unique enhancements bit 0 2 this bit is a read only value indicating whether the group code ?ld in the scsi instruction is standard or vendor unique. if cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. the default for this bit is reset.
5-11 vue1 vendor unique enhancements bit 1 1 this bit is used to disable the automatic byte count reload during block move instructions in the command phase. if this bit is cleared, the device reloads the block move byte count if the ?st byte received is one of the standard group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code. wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) ?g. setting this bit clears the wsr ?g. this clearing function is self-clearing. the wsr ?g indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stored the high-order byte in the scsi wide residue (swide) register rather than passing the byte out the dma channel. the hardware uses the wsr status ?g to determine what behavior must occur at the start of the next data receive transfer. when the ?g is set, the stored data in swide may be ?esidue data, valid data for a subsequent data transfer, or overrun data. the byte is read as normal data by starting a data receive transfer. performing a scsi send operation clears this bit. also, performing any nonwide transfer clears this bit.
5-12 scsi operating registers register: 0x03 (0x83) scsi control three (scntl3) read/write ultra ultra enable 7 setting this bit enables ultra scsi synchronous scsi transfers in systems that have an 80 mhz clock. the default value of this bit is 0. this bit should remain cleared in systems that have a 40 mhz clock, unless the scsi clock doubler is used to increase the sclk frequency to at least 80 mhz. when this bit is set, the signal ?tering period for sreq/ and sack/ automatically changes to 15 ns, regardless of the value of the extend req/ack filtering bit in the scsi test two (stest2) register. scf[2:0] synchronous clock conversion factor [6:4] these bits select a factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. write these to the same value as the clock conversion factor bits below unless fast scsi operation is desired. see the scsi transfer (sxfer) register description for examples of how the scf bits are used to calculate synchronous transfer periods. see the table under the description of bits [7:5] of the scsi transfer (sxfer) register for the valid combinations. note: to migrate from a fast scsi-2 system with a 40 mhz clock, divide the clock by a factor of two or more to achieve the same synchronous transfer rate in a system with an 80 mhz clock. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, ?unctional description. ews enable wide scsi 3 when this bit is clear, all information transfer phases are assumed to be eight bits, transmitted on sd[7:0]/, sdp0/. when this bit is asserted, data transfers are done 16 bits 76 432 0 ultra scf[2:0] ews ccf[2:0] 00000000
5-13 at a time, with the least signi?ant byte on sd[7:0]/, sdp/ and the most signi?ant byte on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. clearing this bit will also clear the wide scsi receive bit in the scsi control two (scntl2) register, which indicates the presence of a valid data byte in the scsi wide residue (swide) register. ccf[2:0] clock conversion factor [2:0] these bits select a factor by which the frequency of sclk is divided before being presented to the scsi core. the synchronous portion of the scsi core can be run at a different clock rate for fast scsi, using the synchronous clock conversion factor bits. the bit encoding is displayed in the table below. all other combinations are reserved and should never be used. note: it is important that these bits be set to the proper values to guarantee that the LSI53C875 meets the scsi timings as de?ed by the ansi speci?ation. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, ?unc- tional description. to migrate from a fast scsi-2 system with a 40 mhz clock, divide the clock by a factor of two or more to achieve the same synchronous transfer rate in a system with an 80 mhz clock. scf2 ccf2 scf1 ccf1 scf0 ccf0 factor frequency scsi clock (mhz) 0 0 0 sclk/3 50.01?5.0 0 0 1 sclk/1 16.67?5.0 0 1 0 sclk/1.5 25.01?7.5 0 1 1 sclk/2 37.51?0.0 1 0 0 sclk/3 50.01?5.0 1 0 1 sclk/4 75.01?0.00 1 1 0 reserved 1 1 1 reserved
5-14 scsi operating registers if the scsi clock doubler is enabled, use the desired frequency after doubling to determine the conversion factor. register: 0x04 (0x84) scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the LSI53C875 is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically recon?ure itself to initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the LSI53C875 is able to respond to bus-initiated selection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically recon?ure itself to target mode as a result of being selected. r reserved 4 enc[3:0] encoded chip scsi id [3:0] these bits are used to store the LSI53C875 encoded scsi id. this is the id which the chip asserts when arbitrating for the scsi bus. the ids that the lsi3c875 responds to when being selected or reselected are con?ured in the response id zero (respid0) and response id one (respid1) registers. the priority of the 16 possible ids, in descending order is: 76543 0 r rre sre r enc x00 x0000 highest lowest 7654321015141312111098
5-15 register: 0x05 (0x85) scsi transfer (sxfer) read/write note: when using table indirect i/o commands, bits [7:0] of this register are loaded from the i/o data structure. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, ?unctional description. tp[2:0] scsi synchronous transfer period [7:5] these bits determine the scsi synchronous transfer period used by the LSI53C875 when sending synchronous scsi data in either initiator or target mode. these bits control the programmable dividers in the chip. note: for ultra scsi transfers, the ideal transfer period is 4, and 5 is acceptable. setting the transfer period to a value greater than 5 is not recommended. the synchronous transfer period the LSI53C875 should use when transferring scsi data is determined as in this example. 754 0 tp[2:0] mo[4:0] 00000000 tp2 tp1 tp0 xferp 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 11
5-16 scsi operating registers the LSI53C875 is connected to a hard disk which can transfer data at 10 mbytes/s synchronously. the LSI53C875s sclk is running at 40 mhz. the synchronous transfer period (sxferp) is found as follows: synchronous send rate = (sclk/scf)/xferp synchronous receive rate = (sckl/scf)/4. where: sclk scsi clock. scf scsi synchronous core frequency. table 5.2 examples of synchronous transfer periods for scsi-1 transfer rates clk (mhz) scsi clk scntl3 bits [6:4] xferp (sxfer) bits [7:5] synch. send rate (mbytes/s) synch. transfer period (ns) synch. receive rate (mbytes) synch. receive period (ns) 80 4 4 5 200 5 200 80 4 5 4 250 5 200 66.67 3 4 5.55 180 5.55 180 66.67 3 5 4.44 225 5.55 180 50 2 4 6.25 160 6.25 160 50 2 5 5 200 6.25 160 40 2 4 5 200 5 200 37.50 1.5 4 6.25 160 6.25 160 33.33 1.5 4 5.55 180 5.55 180 25 1 4 6.25 160 6.25 160 20 1 4 5 200 5 200 16.67 1 4 4.17 240 4.17 240
5-17 mo[4:0] max scsi synchronous offset [4:0] these bits describe the maximum scsi synchronous offset used by the LSI53C875 when transferring synchronous scsi data in either initiator or target mode. table 5.4 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C875. these bits determine the LSI53C875s method of transfer for data-in and data-out phases only. all other information transfers occur asynchronously. table 5.3 example transfer periods for fast scsi-2 and ultra scsi transfer rates clk (mhz) scsi clk scntl3 bits [6:4] xferp synch. send rate (mbytes/s) synch. transfer period (ns) synch. receive rate (mbytes) synch. receive period (ns) 80 1 4 20.0 50 20.0 50 80 2 4 10.0 100 10.0 100 66.67 1.5 4 11.11 90 11.11 90 66.67 1.5 5 8.88 112.5 11.11 90 50 1 4 12.5 80 12.5 80 50 1 5 10.0 100 12.5 80 40 1 4 10.0 100 10.0 100 37.50 1 4 9.375 106.67 9.375 106.67 33.33 1 4 8.33 120 8.33 120 25 1 4 6.25 160 6.25 160 20 1 4 5 200 5 200 16.67 1 4 4.17 240 4.17 240
5-18 scsi operating registers register: 0x06 (0x86) scsi destination id (sdid) read/write r reserved [7:4] enc[3:0] encoded destination scsi id [3:0] writing these bits sets the scsi id of the intended initiator or target during scsi reselection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this table 5.4 maximum synchronous offset mo4 mo3 mo2 mo1 mo0 synchronous offset 00000 0-asynchronous 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 reserved 10010 reserved 10011 reserved 10100 reserved 7430 r enc x x x x0000
5-19 register. the scsi id is de?ed by the user in a scripts select or reselect instruction. the value written should be the binary-encoded id value. the priority of the 16 possible ids, in descending order, is: register: 0x07 (0x87) general purpose (gpreg) read/write r reserved [7:5] gpio[4:0] general purpose [4:0] these bits can be programmed through the general pur- pose pin control (gpcntl) register as inputs, outputs, or to perform special functions. as an output, these pins can be used to enable or disable external terminators. it is also possible to program these signals as live inputs and sense through a scripts register to register move instruction. gpio[3:0] default as inputs and gpio4 defaults as an output pin. when con?ured as inputs, an internal pull-up is enabled. gpio4 can be used to enable or disable v pp , the 12 v power supply to the external ?sh memory. this bit powers up with the power to the external memory disabled. the sdms use of gpio pins sdms software uses gpio3 to detect a differential board. if the pin is pulled low externally, the board is con?ured by sdms software as a differential board. if it is pulled high or left ?ating, sdms software con?ures it as an se board. the lsi logic pci to scsi host adapters use the gpio4 pin in the process of ?shing a new sdms rom. sdms software uses the gpio0 pin to toggle scsi device leds, turning on the led whenever the LSI53C875 is on the scsi bus. sdms highest lowest 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 754 0 r gpio x x x0xxxx
5-20 scsi operating registers software drives this pin low to turn on the led, or drives it high to turn off the led. sdms software uses the gpio[1:0] pins to support serial eeprom access. when serial eeprom access is enabled, gpio1 is used as a clock and gpio0 is used as data. register: 0x08 (0x88) scsi first byte received (sfbr) read/write this register contains the ?st byte received in any asynchronous information transfer phase. for example, when the LSI53C875 is operating in the initiator mode, this register contains the ?st byte received in the message-in, status, and data-in phases. when a block move instruction is executed for a particular phase, the ?st byte received is stored in this register, even if the present phase is the same as the last phase. the ?st byte received or a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read-modify-writes with the scsi first byte received (sfbr) as the destination. this allows bit testing after an operation. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. the load instruction may not be used to write to this register. however, it can be loaded using scripts read/write operations. to load the scsi first byte received (sfbr) with a byte stored in system memory, the byte must ?st be moved to an intermediate LSI53C875 register (such as the scratch register), and then to the scsi first byte received (sfbr) . this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dma control (dcntl) register is clear. 7 0 1b 00000000
5-21 register: 0x09 (0x89) scsi output control latch (socl) read/write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c/d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. socl is used only when transferring data using programmed i/o. some bits are set (1) or reset (0) when executing scsi scripts. do not write to the register once the LSI53C875 starts executing normal scsi scripts. 76543210 req ack bsy sel atn msg c/d i/o 00000000
5-22 scsi operating registers register: 0x0a (0x09) scsi selector id (ssid) read only val scsi valid 7 if val is asserted, then the two scsi ids are detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id is present and the contents of the encoded destination id are meaningless. r reserved [6:4] endid[3:0] encoded destination scsi id [3:0] reading the scsi selector id (ssid) register immediately after the LSI53C875 is selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 speci?ation. this condition is detected by examining the val bit above. register: 0x0b (0x8b) scsi bus control lines (sbcl) read only req sreq/ status 7 ack sack/ status 6 bsy sbsy/ status 5 sel ssel/ status 4 atn satn/ status 3 76 43 0 val r enid 0 x x x0000 76543210 req ack bsy sel atn msg c/d i/o xxxxxxxx
5-23 msg smsg/ status 2 c/d sc_d/ status 1 i/o si_o/ status 0 this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register is used for diagnostics testing or operation in low level mode. register: 0x0c (0x8c) dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts are pending (the LSI53C875 stacks interrupts). the dip bit in the interrupt status (istat) register is also cleared. it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, ?unctional description, for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. 76543210 dfe mdpe bf abrt ssi sir r iid 100000 x0
5-24 scsi operating registers mdpe master data parity error 6 this bit is set when the LSI53C875 as a master detects a data parity error, or a target device signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of chip test four (ctest4) ). bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the LSI53C875 is bus master, and is de?ed as a cycle that ends with a bad address or target abort condition. abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status (istat) register. ssi single step interrupt 3 if the single step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt is generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. ebpi extended byte parity error interrupt 1 (LSI53C875n only) this bit is set whenever the LSI53C875 detects a parity error on one of the four additional parity pins on the LSI53C875n. iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction opcode is detected, whether the LSI53C875 is operating in single step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also set this bit: ? the LSI53C875 is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring.
5-25 ? a block move instruction is executed with 0x000000 loaded into the dma byte counter (dbc) register, indicating that there are zero bytes to move. ? during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the LSI53C875 is in target mode. ? during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. ? a transfer control instruction is executed with the reserved bit 22 set. ? a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode. ? a load/store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. ? a load/store instruction is issued when the register address is not aligned with the memory address. ? a load/store instruction is issued with bit 5 in the dma command (dcmd) register cleared or bits 3 or 2 set. ? a load/store instruction when the count value in the dma byte counter (dbc) register is not set at 1 to 4. ? a load/store instruction attempts to cross a dword boundary. ? a memory move instruction is executed with one of the reserved bits in the dma command (dcmd) register set. ? a memory move instruction is executed with the source and destination addresses not aligned.
5-26 scsi operating registers register: 0x0d (0x8d) scsi status zero (sstat0) read only ilf sidl least signi?ant byte full 7 this bit is set when the least signi?ant byte in the scsi input data latch (sidl) register contains data. data is transferred from the scsi bus to the scsi input data latch (sidl) register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?w through this register. orf sodr least signi?ant byte full 6 this bit is set when the least signi?ant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not readable or writable by the user. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl least signi?ant byte full 5 this bit is set when the least signi?ant byte in the scsi output data latch (sodl) contains data. the scsi out- put data latch (sodl) register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bustothe scsi output data latch (sodl) register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf orf olf aip loa woa rst sdp0/ 00000000
5-27 aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the LSI53C875 has detected a bus free condition, asserted bsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the LSI53C875 has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the sel/ signal. woa won arbitration 2 when set, woa indicates that the LSI53C875 has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst/ scsi rst/ signal 1 this bit reports the current status of the scsi rst/ signal, and the rst signal (bit 6) in the interrupt status (istat) register. this bit is not latched and may change as it is read. sdp0/ scsi sdp0/ parity signal 0 this bit represents the active high current status of the scsi sdp0/ parity signal. this signal is not latched and may change as it is read. register: 0x0e (0x8e) scsi status one (sstat1) read only ff[3:0] fifo flags [7:4] these four bits, along with scsi status two (sstat2) , bit 4, de?e the number of bytes or words that currently reside in the LSI53C875s scsi synchronous data fifo and shown in table 5.5 . these bits are not latched and they will change as data moves through the fifo. 7 43210 ff[3:0] sdp0l msg c/d i/o 0000xxxx
5-28 scsi operating registers sdp0l latched scsi parity 3 this bit re?cts the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch (sidl) . it changes when a new byte is latched into the least signi?ant byte of the scsi input data latch (sidl) register. this bit is active high, in other words, it is set when the parity signal is active. msg scsi msg/ signal 2 c/d scsi c_d/ signal 1 i/o scsi i_o/ signal 0 these scsi phase status bits are latched on the asserting edge of sreq/ when operating in either initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in low level mode. table 5.5 scsi synchronous data fifo word count ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 0 1101 13 0 1110 14 0 1111 15 1 0000 16
5-29 register: 0x0f (0x8f) scsi status two (sstat2) read only ilf1 sidl most signi?ant byte full 7 this bit is set when the most signi?ant byte in the scsi input data latch (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?w through this register. orf1 sodr most signi?ant byte full 6 this bit is set when the most signi?ant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not accessible to the user. this bit is used to determine how many bytes reside in the chip when an error occurs. olf1 sodl most signi?ant byte full 5 this bit is set when the most signi?ant byte in the scsi output data latch (sodl) contains data. the scsi out- put data latch (sodl) register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bustothe scsi output data latch (sodl) register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf1 orf1 olf1 ff4 spl1 r ldsc sdp1 0000x x1x
5-30 scsi operating registers ff4 fifo flags bit 4 4 this is the most signi?ant bit in the scsi fifo flags ?ld, with the rest of the bits in scsi status one (sstat1) . for a complete description of this ?ld, see the de?ition for scsi status one (sstat1) , bits [7:4]. spl1 latched scsi parity for sd[15:8] 3 this active high bit re?cts the scsi odd parity signal corresponding to the data latched into the most signi?ant byte in the scsi input data latch (sidl) register. r reserved 2 ldsc last disconnect 1 this bit is used in conjunction with the connected (con) bit in scsi control one (scntl1) . it allows the user to detect the case in which a target device disconnects, and then some scsi device selects or reselects the LSI53C875. if the connected bit is asserted and the ldsc bit is asserted, a disconnect is indicated. this bit is set when the connected bit in scsi control one (scntl1) is off. this bit is cleared when a block move instruction is executed while the connected bit in scsi control one (scntl1) is on. sdp1 scsi sdp1 signal 0 this bit represents the active high current state of the scsi sdp1 parity signal. it is unlatched and may change as it is read.
5-31 registers: 0x10?x13 (0x90?x93) data structure address (dsa) read/write dsa data structure address [31:0] this 32-bit register contains the base address used for all table indirect calculations. the data structure address (dsa) register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x14 (0x94) interrupt status (istat) read/write this register is accessible by the host cpu while the LSI53C875 is executing scripts (without interfering in the operation of the function). it is used to poll for interrupts if hardware interrupts are disabled. read this register after servicing an interrupt to check for stacked interrupts. for more information on interrupt handling refer to chapter 2, ?unctional description. abrt abort operation 7 setting this bit aborts the current operation under execution by the LSI53C875. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 31 0 dsa[31:0] 00000000000000000000000000000000 76543210 abrt srst sigp sem con intf sip dip 00000000
5-32 scsi operating registers 2. wait for an interrupt. 3. read the interrupt status (istat) register. 4. if the scsi interrupt pending bit is set, then read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause of the scsi interrupt and go back to step 2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 0x00 value to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. srst software reset 6 setting this bit resets the LSI53C875. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this reset does not clear the lsi53c700 family compatibility bit or any of the pci con?uration registers. this bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). sigp signal process 5 sigp is a r/w bit that can be written at any time, and polled and reset using chip test two (ctest2) . the sigp bit is used in various ways to pass a ?g to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 the scripts processor may set this bit using a scripts register write instruction. an external processor may also set is while the LSI53C875 is executing a scripts operation. this bit enables the LSI53C875 to
5-33 notify an external processor of a prede?ed condition while scripts are running. the external processor may also notify the LSI53C875 of a prede?ed condition and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the LSI53C875 is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the LSI53C875 responds to a bus-initiated selection or reselection. it is also set after the LSI53C875 wins arbitration when operating in low level mode. when this bit is clear, the LSI53C875 is not connected to the scsi bus. intf interrupt-on-the-fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set when the interrupt status (istat) register is read it is not automatically cleared. to clear this bit, write it to a one. the reset operation is self-clearing. if the intf bit is set but sip or dip are not set, do not attempt to read the other chip status registers. an interrupt-on-the-fly interrupt must be cleared before servicing any other interrupts indicated by sip or dip. this bit must be written to one in order to clear it after it has been set. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the LSI53C875. the following conditions cause a scsi interrupt to occur: ? a phase mismatch (initiator mode) or satn/ becomes active (target mode) ? an arbitration sequence completes ? a selection or reselection time-out occurs ? the LSI53C875 is selected
5-34 scsi operating registers ? the LSI53C875 is reselected ? a scsi gross error occurs ? an unexpected disconnect occurs ? a scsi reset occurs ? a parity error is detected ? the handshake-to-handshake timer is expired ? the general purpose timer is expired to determine exactly which condition(s) caused the interrupt, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the LSI53C875. the following conditions cause a dma interrupt to occur: ? a pci parity error is detected ? a bus fault is detected ? an abort condition is detected ? a scripts instruction is executed in single step mode ? a scripts interrupt instruction is executed ? an illegal instruction is detected to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register. register: 0x18 (0x98) chip test zero (ctest0) read/write fmt byte empty in dma fifo [7:0] this was a general purpose read/write register in previous lsi53c8xx family chips. although it is still a read/write register, lsi logic reserves the right to use these bits for future lsi53c8xx family enhancements. 7 0 fmt 11111111
5-35 register: 0x19 (0x99) chip test one (ctest1) read only fmt[3:0] byte empty in dma fifo [7:4] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 is set. since the fmt ?gs indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. ffl[3:0] byte full in dma fifo [3:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 is set. since the ffl ?gs indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. register: 0x1a (0x9a) chip test two (ctest2) read/write ddir data transfer direction 7 this status bit indicates which direction data is being transferred. when this bit is set, the data is transferred from the scsi bus to the host bus. when this bit is clear, the data is transferred from the host bus to the scsi bus. 7430 fmt[3:0] ffl[3:0] 11110000 76543210 ddir sigp cio cm srtch teop dreq dack 00xx0001
5-36 scsi operating registers sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status (istat) register (bit 5). the sigp bit is used to signal a running scripts instruction. when this register is read, the sigp bit in the interrupt status (istat) register is cleared. cio con?ured as i/o 5 this bit is de?ed as the con?uration i/o enable status bit. this read only bit indicates if the chip is currently enabled as i/o space. both bits 4 and 5 are set if the chip is dual-mapped. cm con?ured as memory 4 this bit is de?ed as the con?uration memory enable status bit. this read only bit indicates if the chip is currently enabled as memory space. both bits 4 and 5 are set if the chip is dual-mapped. srtch scratcha/b operation 3 this bit controls the operation of the scratch register a (scratcha) and scratch register b (scratchb) registers. when it is set, scratchb contains the ram base address value from the pci con?uration ram base address register. this is the base address for the 4 kbyte internal ram. in addition, the scratch register a (scratcha) register displays the memory mapped based address of the chip operating registers. when this bit is cleared, the scratch register a (scratcha) and scratch register b (scratchb) registers return to normal operation. note: bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify-write to this register. teop scsi true end of process 2 this bit indicates the status of the LSI53C875s internal teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the LSI53C875. when this bit is set, teop is active. when this bit is clear, teop is inactive.
5-37 dreq data request status 1 this bit indicates the status of the LSI53C875s internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive. dack data acknowledge status 0 this bit indicates the status of the LSI53C875s internal data acknowledge signal (dack/). when this bit is set, dack/ is inactive. when this bit is clear, dack/ is active. register: 0x1b (0x9b) chip test three (ctest3) read/write v[3:0] chip revision level [7:4] these bits identify the chip revision level for software purposes. the value should be the same as the lower nibble of the pci revision id register, at address 0x08 in con?uration space. flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma next address (dnad) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C875. polling of fifo ?gs is allowed during ?sh operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. after the LSI53C875 successfully clears the appropriate fifo pointers and registers, this bit automatically clears. this bit does not clear the data visible at the bottom of the fifo. 7 43210 v flf clf fm wrie xxxx0000
5-38 scsi operating registers fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the opcode portion of an instruction fetch. this allows the storage of scripts in a prom while data tables are stored in ram. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. wrie write and invalidate enable 0 this bit, when set, causes the issuing of memory write and invalidate commands on the pci bus whenever legal. these conditions are described in detail in chapter 3, ?ci functional description. registers: 0x1c?x1f (0x9c?x9f) temporary (temp) read/write temp temporary [31:0] this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dma scripts pointer (dsp) register when a return instruction is executed. this address points to the next instruction to execute. do not write to this register while the LSI53C875 is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. 31 0 temp xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-39 register: 0x20 (0xa0) dma fifo (dfifo) read/write bo[7:0] byte offset counter [7:0] these bits, along with bits [1:0] in the chip test five (ctest5) register, indicate the amount of data transferred between the scsi core and the dma core. it is used to determine the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. the dma fifo (dfifo) register counts the number of bytes transferred between the dma core and the scsi core. the dma byte counter (dbc) register counts the number of bytes transferred across the host bus. the difference between these two counters represents the number of bytes remaining in the dma fifo. the following steps determine how many bytes are left in the dma fifo when an error occurs, regardless of the transfer direction: if the dma fifo size is set to 88 bytes: 1. subtract the seven least signi?ant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. 2. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?ant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. 7 0 bo x0000000
5-40 scsi operating registers 3. if the dma fifo size is set to 88 bytes, and the result with 0x7f for a byte count between 0 and 64. if the dma fifo size is set to 536 bytes, and the result with 0x3ff for a byte count between 0 and 536. note: to calculate the total number of bytes in both the dma fifo and scsi logic, see the section on data paths in chapter 2, ?unctional description. register: 0x21 (0xa1) chip test four (ctest4) read/write bdis burst disable 7 when set, this bit causes the LSI53C875 to perform back-to-back cycles for all transfers. when this bit is cleared, LSI53C875 back-to-back transfers for opcode fetches and burst transfers for data moves are per- formed. zmod high impedance mode 6 setting this bit causes the LSI53C875 to place all output and bidirectional pins into a high impedance state. in order to read data out of the LSI53C875, clear this bit. this bit is intended for board-level testing only. do not set this bit during normal system operation. zsd scsi data high impedance 5 setting this bit causes the LSI53C875 to place the scsi data bus sd[15:0] and the parity lines sdp[1:0] in a high impedance state. in order to transfer data on the scsi bus, clear this bit. srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory-to-memory move operations. when this bit is set, register accesses to the temporary (temp) and data structure address (dsa) registers are directed to 765432 0 bdis zmod zsd srtm mpee fbl[2:0] 00000000
5-41 the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to-memory move operation. the data structure address (dsa) and temporary (temp) registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the LSI53C875. a parity error during a bus master write is detected by the target, and the LSI53C875 is informed of the error by the perr/ pin being asserted by the target. when this bit is cleared, the LSI53C875 does not interrupt if a master parity error occurs. this bit is cleared at power-up. fbl[2:0] fifo byte control [2:0] these bits steer the contents of the chip test six (ctest6) register to the appropriate byte lane of the 32-bit dma fifo. if the fbl2 bit is set, then fbl1 and fbl0 determine which of four byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dma next address (dnad) and dma byte counter (dbc) registers. each of the four bytes that make up the 32-bit dma fifo is accessed by writing these bits to the proper value. for normal operation, fbl2 must equal zero. fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x disabled n/a 1 0 0 0 d[7:0] 1 0 0 1 d[15:8] 1 0 1 2 d[23:16] 1 0 1 3 d[31:24]
5-42 scsi operating registers register: 0x22 (0xa2) chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next address (dnad) register. the dma next address (dnad) register is incremented based on the dnad contents and the current dbc value. this bit automatically clears itself after incrementing the dma next address (dnad) register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dma byte counter (dbc) register. it is decremented based on the dbc contents and the current dnad value. this bit automatically clears itself after decrementing the dma byte counter (dbc) register. dfs dma fifo size 5 this bit controls the size of the dma fifo. when clear, the dma fifo appears as only 88 bytes deep. when set, the dma fifo size increases to 536 bytes. using an 88-byte fifo allows software written for other lsi53c8xx family chips to properly calculate the number of bytes residing in the chip after a target disconnect. the default value of this bit is zero. masr master control for set or reset pulses 4 this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is cleared, bit 3 deasserts the corresponding signals. do not change this bit and bit 3 in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting 76543210 adck bbck dfs masr ddir bl2 bo[9:8] 00000xxx
5-43 the dmawr signal indicates that data is transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. bl2 burst length 2 this bit works with bits 6 and 7 in the dma mode (dmode) register to determine the burst length. for complete de?itions of this ?ld, refer to the descriptions of dma mode (dmode) bits 6 and 7. this bit is disabled if an 88-byte fifo is selected by clearing the dma fifo size bit. bo[9:8] byte offset [1:0] these are the upper two bits of the dma fifo byte offset counter. the entire ?ld is described under the dma fifo (dfifo) register, bits [7:0]. register: 0x23 (0xa3) chip test six (ctest6) read/write df[7:0] dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts operation. write this register only when testing the dma fifo using the chip test four (ctest4) register. writes to this register while the test mode is not enabled produces unexpected results. 7 0 df 00000000
5-44 scsi operating registers registers: 0x24?x26 (0xa4?xa6) dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the LSI53C875. the dbc counter is decremented each time data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that are transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dma byte counter (dbc) register, an illegal instruction interrupt occurs if the LSI53C875 is not in target mode, command phase. the dma byte counter (dbc) register is also used to hold the least signi?ant 24 bits of the ?st dword of a scripts fetch, and to hold the offset value during table indirect i/o scripts. for a complete description, see chapter 6, ?nstruction set of the i/o processor. the power-up value of this register is indeterminate. 23 0 dbc xxxxxxxxxxxxxxxxxxxxxxxx
5-45 register: 0x27 (0xa7) dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the LSI53C875 to execute. this register has a different format for each instruction. for complete descriptions, see chapter 6, ?nstruction set of the i/o processor. registers: 0x28?x2b (0xa8?xab) dma next address (dnad) read/write dnad dma next address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dsps register. its value may not be valid except in certain abort conditions. the default value of this register is zero. do not use this register to determine data addresses during a phase mismatch interrupt, as its value is not always correct for this use. use the dma byte counter (dbc) , dma fifo (dfifo) , and dma scripts pointer save (dsps) registers to calculate residual byte counts and addresses as described in section 2.5.8.1, ?ata paths, in chapter 2, ?unctional description. 7 0 dcmd xxxxxxxx 31 0 dnad 00000000000000000000000000000000
5-46 scsi operating registers registers: 0x2c?x2f (0xac?xaf) dma scripts pointer (dsp) read/write dsp dma scripts pointer [31:0] to execute scsi scripts, the address of the ?st scripts instruction must be written to this register. in normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in single step mode, there is a single step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address, but the start dma bit (bit 2, dma control (dcntl) register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero. registers: 0x30?x33 (0xb0?xb3) dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [31:0] this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. 31 0 dsp 00000000000000000000000000000000 31 0 dsps xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-47 registers: 0x34?x37 (0xb4?xb7) scratch register a (scratcha) read/write scratcha scratch register a [31:0] this is a general purpose, user-de?able scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register alter its contents. the LSI53C875 cannot fetch scripts instructions from this location. when bit 3 in the chip test two (ctest2) register is set, this register contains the memory-mapped base address of the operating registers. setting chip test two (ctest2) bit 3 only causes the base address to appear in this register. any information that was previously in the register remains intact. any writes to this register while chip test two (ctest2), bit 3 is set passes through to the actual scratch register a (scratcha) register. the power-up value of this register is indeterminate. register: 0x38 (0xb8) dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of transfers performed per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. the LSI53C875 asserts the bus request (req/) output when the dma fifo can accommodate a transfer of at least one burst size of data. bus request (req/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. the LSI53C875 inserts a fairness delay of four clks between burst length transfers (as 31 0 scratcha xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 76543210 bl[1:0] siom diom erl ermp bof man 00000000
5-48 scsi operating registers set in bl[1:0]) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. siom source i/o-memory enable 5 this bit is de?ed as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; and if cleared, then the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when the LSI53C875 is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?uration status of the LSI53C875. diom destination i/o-memory enable 4 this bit is de?ed as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; and if cleared, then the destination address is in memory space. this function is useful for memory- to- register operations using the memory move instruction when the LSI53C875 is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?uration status of the LSI53C875. bl2 (ctest5 bit 2) bl1 bl0 burst length transfers 0002 0014 0108 01116 10032 1 10164 1 1 1 0 128 1 1 1 1 reserved 1. only valid if the fifo size is set to 536 bytes.
5-49 erl enable read line 3 this bit enables a pci read line command. if pci cache mode is enabled by setting bits in the pci cache line size register, this chip issues a read line command on all read cycles if other conditions are met. for more information on these conditions, refer to chapter 3, ?ci functional description. ermp enable read multiple 2 this bit causes read multiple commands to be issued on the pci bus after certain conditions have been met. these conditions are described in chapter 3, ?ci func- tional description. bof burst opcode fetch enable 1 setting this bit causes the LSI53C875 to fetch instructions in burst mode. speci?ally, the chip bursts in the ?st two dwords of all instructions using a single bus ownership. if the instruction is a memory-to-memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. this bit has no effect if scripts instruction prefetching is enabled. man manual start mode 0 setting this bit prevents the LSI53C875 from automatically fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. when this bit is set, the start dma bit in the dma control (dcntl) register must be set to begin scripts execution. clearing this bit causes the LSI53C875 to automatically begin fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. this bit normally is not used for scsi scripts operations.
5-50 scsi operating registers register: 0x39 (0xb9) dma interrupt enable (dien) read/write r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single-step interrupt 3 sir scripts interrupt instruction received 2 ebpe extended byte parity enable 1 (LSI53C875n only) iid illegal instruction detected 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit is still set in the dma status (dstat) register. masking an interrupt does not prevent the istat dip from being set. all dma interrupts are considered fatal, therefore scripts stops running when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of irq/ for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the istat sip or dip bit is set.) the irq/ output is latched. once asserted, it will remain asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is asserted does not cause deassertion of irq/. 76543210 r mdpe bf abrt ssi sir r iid x00000 x0
5-51 for more information on interrupts, see chapter 2, ?unctional description. register: 0x3a (0xba) scratch byte register (sbr) read/write this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register will alter its contents. the default value of this register is zero. this register was called the dma watchdog timer on previous lsi53c8xx family products. register: 0x3b (0xbb) dma control (dcntl) read/write clse cache line size enable 7 setting this bit enables the LSI53C875 to sense and react to cache line boundaries set up by the dmode or pci cache line size register, whichever contains the smaller value. clearing this bit disables the cache line size logic and the LSI53C875 monitors the cache line size using the dma mode (dmode) register. pff prefetch flush 6 setting this bit causes the prefetch unit to ?sh its contents. the bit clears after the ?sh is complete. pfen prefetch enable 5 setting this bit enables the prefetch unit if the burst size is equal to or greater than four. for more information on scripts instruction prefetching, see chapter 2, ?unc- tional description. ssm single step mode 4 setting this bit causes the LSI53C875 to stop after executing each scripts instruction, and generates a single step interrupt. when this bit is cleared, the LSI53C875 does not stop after each instruction. it 76543210 clse pff pfen ssm irqm std irqd com 00000000
5-52 scsi operating registers continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit clear. to restart the LSI53C875 after it generates a scripts step interrupt, read the interrupt status (istat) and dma status (dstat) registers to recognize and clear the interrupt. then set the start dma bit in this register. irqm irq mode 3 when set, this bit will enable a totem pole driver for the irq pin. when cleared, this bit enables an open drain driver for the irq pin with a internal weak pull-up. this bit is reset at power up. the bit should remain cleared to retain full pci compliance. std start dma operation 2 the LSI53C875 fetches a scsi scripts instruction from the address contained in the dma scripts pointer (dsp) register when this bit is set. this bit is required if the LSI53C875 is in one of the following modes: ? manual start mode bit 0 in the dma mode (dmode) register is set ? single step mode bit 4 in the dma control (dcntl) register is set when the LSI53C875 is executing scripts in manual start mode, the start dma bit must to be set to start instruction fetches, but need not be set again until an interrupt occurs. when the LSI53C875 is in single step mode, the start dma bit needs to be set to restart execution of scripts after a single step interrupt. irqd irq disable 1 setting this bit disables the irq pin. clearing the bit enables normal operation. as with any other register other than istat, this register cannot be accessed except by a scripts instruction during scripts exe- cution. for more information on the use of this bit in inter- rupt handling, see chapter 2, ?unctional description.
5-53 com lsi53c700 family compatibility 0 when the com bit is cleared, the LSI53C875 behaves in a manner compatible with the lsi53c700 family; selection/reselection ids are stored in both the scsi selector id (ssid) and scsi first byte received (sfbr) registers. when this bit is set, the id is stored only in the scsi selector id (ssid) register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register-to-register operation. this bit is not affected by a software reset. register: 0x3c?x3f (0xbc?xbf) adder sum output (adder) read only adder adder sum output [31:0] this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. register: 0x40 (0xc0) scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status zero (sist0) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, see chapter 2, ?unctional description. 31 0 adder xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 76543210 m/a cmp sel rsl sge udc rst par 00000000
5-54 scsi operating registers m/a scsi phase mismatch - initiator mode; 7 scsi atn condition - target mode in initiator mode, this bit is set when the scsi phase asserted by the target and sampled during sreq/ does not match the expected phase in the scsi output control latch (socl) register. this expected phase is automatically written by scsi scripts. in target mode, this bit is set when the initiator has asserted satn/. see the disable halt on parity error or satn/ condition bit in the scsi control one (scntl1) register for more information on when this status is actually raised. cmp function complete 6 full arbitration and selection sequence is completed. sel selected 5 indicates the LSI53C875 is selected by a scsi target device. set the enable response to selection bit in the scsi chip id (scid) register for this to occur. rsl reselected 4 indicates the LSI53C875 is reselected by a scsi initiator device. set the enable response to reselection bit in the scsi chip id (scid) register for this to occur. sge scsi gross error 3 the following conditions are considered scsi gross errors: ? data under?w reading the scsi fifo when no data is present. ? data over?w writing to the scsi fifo while it is full. ? offset under?w receiving an sack/ pulse in target mode before the corresponding sreq/ is set. ? offset over?w receiving an sreq/ pulse in the initiator mode, and exceeding the maximum offset (de?ed by the mo[3:0] bits in the scsi transfer (sxfer) register). ? a phase change in the initiator mode, with an outstanding sreq/sack/ offset.
5-55 ? residual data in scsi fifo starting a transfer other than synchronous data receive with data left in the scsi synchronous receive fifo. udc unexpected disconnect 2 this condition only occurs in the initiator mode. it happens when the target to which the LSI53C875 is connected disconnects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scsi control two (scntl2) register for more information on expected versus unexpected disconnects. any discon- nect in low level mode causes this condition. rst scsi reset condition 1 indicates assertion of the srst/ signal by the LSI53C875 or any other scsi device. this condition is edge- triggered, so multiple interrupts cannot occur because of a single srst/ pulse. par scsi parity error 0 indicates detection of a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scsi control one (scntl1) register for more information on when this condition is actually raised. register: 0x41 (0xc1) scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status one (sist1) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, refer to chapter 2, ?unctional description. 7 3210 r sto gen hth x x x x x000
5-56 scsi operating registers r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C875 is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register bits [3:0] for more information on the time-out timer. gen general purpose timer expired 1 the general purpose timer is expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 the handshake-to-handshake timer is expired. the time measured is the scsi request-to-request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to- handshake timer. register: 0x42 (0xc2) scsi interrupt status zero (sist0) read only reading the scsi interrupt status zero (sist0) register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable zero (sien0) register or not. each bit set indicates occurrence of the corresponding condition. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C875 stacks interrupts). scsi interrupt conditions are individually masked through the scsi interrupt enable zero (sien0) register. 76543210 m/a cmp sel rsl sge udc rst par 00000000
5-57 when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the istat sip and dip bits may not be set, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers before the dma status (dstat) register to avoid missing a scsi interrupt. for more information on interrupts, refer to chapter 2, ?unctional description. m/a initiator mode: phase mismatch; 7 target mode: satn/ active in initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. sel selected 5 this bit is set when the LSI53C875 is selected by another scsi device. the enable response to selection bit must be set in the scsi chip id (scid) register (and the respid register must hold the chips id) for the LSI53C875 to respond to selection attempts. rsl reselected 4 this bit is set when the LSI53C875 is reselected by another scsi device. the enable response to reselection bit must be set in the scsi chip id (scid) register (and the respid register must hold the chips id) for the LSI53C875 to respond to reselection attempts. sge scsi gross error 3 this bit is set when the LSI53C875 encounters a scsi gross error condition. the following conditions can result in a scsi gross error condition: ? data under?w reading the scsi fifo when no data is present.
5-58 scsi operating registers ? data over?w writing too many bytes to the scsi fifo, or the synchronous offset causes overwriting the scsi fifo. ? offset under?w the LSI53C875 is operating in target mode and a sack/ pulse is received when the outstanding offset is zero. ? offset over?w the other scsi device sends a sreq/ or sack/ pulse with data which exceeds the maximum synchronous offset de?ed by the scsi transfer (sxfer) register. ? a phase change occurs with an outstanding synchronous offset when the LSI53C875 is operating as an initiator. ? residual data in the synchronous data fifo a transfer other than synchronous data receive is started with data left in the synchronous data fifo. udc unexpected disconnect 2 this bit is set when the LSI53C875 is operating in the initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the LSI53C875 operates in the initiator mode. when the LSI53C875 operates in low level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect). rst scsi rst/ received 1 this bit is set when the LSI53C875 detects an active srst/ signal, whether the reset is generated external to the chip or caused by the assert srst/ bit in the scsi control one (scntl1) register. the scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. par parity error 0 this bit is set when the LSI53C875 detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scsi control zero (scntl0) register) must be set for this bit to become active. the LSI53C875 always generates parity when sending scsi data.
5-59 register: 0x43 (0xc3) scsi interrupt status one (sist1) read only reading the scsi interrupt status one (sist1) register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable one (sien1) register or not. each bit that is set indicates an occurrence of the corresponding condition. reading the scsi interrupt status one (sist1) clears the interrupt condition. r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C875 is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more information on the time-out timer. gen general purpose timer expired 1 this bit is set when the general purpose timer expires. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer expires. the time measured is the scsi request-to- request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. 7 3210 r sto gen hth x x x x x000
5-60 scsi operating registers register: 0x44 (0xc4) scsi longitudinal parity (slpar) read/write slpar scsi longitudinal parity [7:0] the scsi longitudinal parity (slpar) register consists of two multiplexed bytes; other register bit settings determine what is displayed at this memory location at any given time. when bit 5 in the scsi control two (scntl2) (slpmd) register is cleared, the chip xors the high and low bytes of the scsi longitudinal parity (slpar) register together to give a single byte value which is displayed in the scsi longitudinal parity (slpar) register. if the slpmd bit is set, then the scsi longitudinal parity (slpar) register shows either the high byte or the low byte of the slpar word. the slpar high byte enable bit, scsi control two (scntl2) bit 4, determines which byte of the scsi longitudinal parity (slpar) register is visible on the scsi longitudinal par- ity (slpar) register at any given time. if this bit is cleared, the scsi longitudinal parity (slpar) register contains the low byte of the slpar word; if it is set, the scsi longitudinal parity (slpar) register contains the high byte of the slpar word. this register performs a bytewise longitudinal parity check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, scsi longitudinal parity (slpar) should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one check byte are received from the scsi bus (all signals are shown active high): 7 0 slpar xxxxxxxx
5-61 a one in any bit position of the ?al slpar value would indicate a transmission error. the scsi longitudinal parity (slpar) register is also used to generate the check bytes for scsi send operations. if the scsi longitudinal parity (slpar) register contains all zeros prior to sending a block move, it contains the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register resets it to zero. the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. register: 0x45 (0xc5) scsi wide residue (swide) read/write swide scsi wide residue [7:0] after a wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the ?st data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore data bytes running slpar 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity 4. 10010110 00000000 7 0 swide xxxxxxxx
5-62 scsi operating registers wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate. register: 0x46 (0xc6) memory access control (macntl) read/write typ[3:0] chip type [7:4] these bits identify the chip type for software purposes. this technical manual applies to devices that have these bits set to 0x07. bits 3 through 0 of this register are used to determine if an external bus master access is to local or far memory. when bits 3 through 0 are set, the corresponding access is considered local and the mac/_testout pin is driven high. when these bits are clear, the corresponding access is to far memory and the mac/_testout pin is driven low. this function is enabled after a transfer control scripts instruction is executed. dwr datawr 3 this bit is used to de?e if a data write is considered to be a local memory access. drd datard 2 this bit is used to de?e if a data read is considered to be a local memory access. pscpt pointer scripts 1 this bit is used to de?e if a pointer to a scripts indirect or table indirect fetch is considered to be a local memory access. scpts scripts 0 this bit is used to de?e if a scripts fetch is considered to be a local memory access. 7 43210 typ dwr drd pscpt scpts 11110000
5-63 register: 0x47 (0xc7) general purpose pin control (gpcntl) read/write this register is used to determine if the pins controlled by the general purpose (gpreg) register are inputs or outputs. bits [4:0] in gpcntl correspond to bits [4:0] in the general purpose (gpreg) register. when the bits are enabled as inputs, an internal pull-up is also enabled. me master enable 7 the internal bus master signal is presented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1_en). fe fetch enable 6 the internal opcode fetch signal is presented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0_en). r reserved 5 gpio4_en[4:2] gpio enable [4:2] the general purpose control, corresponding to bits [4:2] in the general purpose (gpreg) register and pins 60, 59, and 57. gpio4 powers up as a general purpose output, and gpio[3:2] power-up as general purpose inputs. gpio1_en[1:0] gpio enable [1:0] these bits power-up set, causing the gpio1 and gpio0 pins to become inputs. clearing these bits causes gpio[1:0] to become outputs. 7654 210 me fe r gpio gpio 00 x01111
5-64 scsi operating registers register: 0x48 (0xc8) scsi timer zero (stime0) read/write hth handshake-to-handshake timer period [7:4] these bits select the handshake-to-handshake time-out period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the scsi interrupt status one (sist1) register is set. the following table contains time-out periods for the handshake-to-handshake timer, the selection/reselection timer (bits [3:0]), and the general purpose timer ( scsi timer one (stime1) , bits [3:0]. for a more detailed explanation of interrupts, refer to chapter 2, ?unctional description. 7430 hth[3:0] sel[3:0] 00000000
5-65 sel selection time-out [3:0] these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 s selection abort time) is exceeded, the sto bit in the scsi interrupt sta- tus one (sist1) register is set. for a more detailed explanation of interrupts, refer to chapter 2, ?unctional description. hth [7:4] sel [3:0] gen [3:0] minimum time-out 1 1. these values will be correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. 40 mhz/80 mhz 50 mhz 0000 disabled disabled 0001 125 s 100 s 0010 250 s 200 s 0011 500 s 400 s 0100 1 ms 800 s 0101 2 ms 1.6 ms 0110 4 ms 3.2 ms 0111 8 ms 6.4 ms 1000 16 ms 12.8 ms 1001 32 ms 25.6 ms 1010 64 ms 51.2 ms 1011 128 ms 102.4 ms 1100 256 ms 204.8 ms 1101 512 ms 409.6 ms 1110 1.024 s 819.2 ms 1111 2.048 s 1.6384 s
5-66 scsi operating registers register: 0x49 (0xc9) scsi timer one (stime1) read/write r reserved 7 hthba handshake-to-handshake timer bus 6 activity enable setting this bit causes this timer to begin testing for scsi req/ack activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. gensf general purpose timer scale factor 5 setting this bit causes this timer to shift by a factor of 16. 76543 0 r hthba gensf hthsf gen[3:0] x0000000
5-67 hth [7:4] sel [3:0] gen [3:0] minimum time-out 1 (50 mhz clock) 1. these values will be correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. gensf = 0 gensf = 1 0000 disabled disabled 0001 100 s 1.6 ms 0010 200 s 3.2 ms 0011 400 s 6.4 ms 0100 800 s 12.8 ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 s 1100 204.8 ms 3.2 s 1101 409.6 ms 6.4 s 1110 819.2 ms 12.8 s 1111 1.6 s 25.6 s
5-68 scsi operating registers hthsf handshake-to-handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the hth [7:4] sel [3:0] gen [3:0] minimum time-out 1 (80 mhz clock) 1. these values will be correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. gensf = 0 gensf = 1 0000 disabled disabled 0001 125 s2ms 0010 250 s4ms 0011 500 s8ms 0100 1 s16ms 0101 2 ms 32 ms 0110 4 ms 64 ms 0111 8 ms 128 ms 1000 16 ms 256 ms 1001 32 ms 512 ms 1010 64 ms 1 s 1011 128 ms 2 s 1100 256 ms 4.1 s 1101 512 ms 8.2 s 1110 1.024 s 16.4 s 1111 2.048 s 32.8 s
5-69 gen bit in the scsi interrupt status one (sist1) register is set. refer to the table under scsi timer zero (stime0) , bits [3:0], for the available time-out periods. note: to reset a timer before it expires and obtain repeatable delays, the time value must be written to zero ?st, and then written back to the desired value. this is also required when changing from one time value to another. see chapter 2, ?unctional description, for an explanation of how interrupts are generated when the timers expire. register: 0x4a (0xca) response id zero (respid0) read/write respid0 response id zero [7:0] respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?ant bit of respid1 representing id 15 and the least signi?ant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the response id one (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. 7 0 id xxxxxxxx
5-70 scsi operating registers register: 0x4b (0xcb) response id one (respid1) read/write respid1 response id one [15:8] respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?ant bit of respid1 representing id 15 and the least signi?ant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the response id one (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4c (0xcc) scsi test zero (stest0) read only ssaid scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the LSI53C875 is selected or reselected as during a scsi selection or reselection phase. these bits are read only and contain the encoded value of 0?5 possible ids that are used to select the LSI53C875. during a scsi selection or reselection phase, when a valid id has been put on the bus, and the LSI53C875 responds to that id, the ?elected as id is written into these bits. these bits are used with the respid registers to allow response to multiple ids on the bus. 15 8 id xxxxxxxx 7 43210 ssaid slt art soz som 00000x11
5-71 slt selection response logic test 3 this bit is set when the LSI53C875 is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the LSI53C875 exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing, but it may be used during low level mode operation to determine if the LSI53C875 has won arbitration. soz scsi synchronous offset zero 1 this bit indicates that the current synchronous sreq/sack offset is zero. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C875, functioning as an initiator, is waiting for the target to request data transfers. if the LSI53C875 is a target, then the initiator has sent the offset number of acknowledges. som scsi synchronous offset maximum 0 this bit indicates that the current synchronous sreq/sack offset is the maximum speci?d by bits [3:0] in the scsi transfer (sxfer) register. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C875, as a target, is waiting for the initiator to acknowledge the data transfers. if the LSI53C875 is an initiator, then the target has sent the offset number of requests.
5-72 scsi operating registers register: 0x4d (0xcd) scsi test one (stest1) read/write sclk scsi clock 7 when set, this bit disables the external sclk (scsi clock) pin, and the chip uses the pci clock as the internal scsi clock. if a transfer rate of 10 mbytes/s (or 20 mbytes/s on a wide scsi bus) is desired on the scsi bus, this bit must be cleared and a 40 mhz external sclk must be provided. siso scsi isolation mode 6 this bit allows the LSI53C875 to put the scsi bidirectional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. r reserved [5:4] dblen doubler enable 3 set this bit to bring the scsi clock doubler out of the powered-down state. the default value of this bit is clear (scsi clock doubler powered down). set bit 2 after setting this bit, to double the sclk frequency. dblsel doubler select 2 set this bit after powering up the scsi clock doubler to double the sclk frequency. this bit has no effect unless bit 3 is set. r reserved [1:0] 5.0.0.1 doubling the scsi clk frequency the LSI53C875 scsi clock doubler doubles a 40 mhz scsi clock, increasing the frequency to 80 mhz. follow these steps to use the clock doubler: 1. set the sclk doubler enable bit ( scsi test one (stest1) , bit 3). 76543210 sclk siso r dblen dblsel r 00 x x00 x x
5-73 2. wait 20 s. 3. halt the scsi clock by setting the halt scsi clock bit ( scsi test three (stest3) , bit 5). 4. set the clock conversion factor using the scf and ccf ?lds in the scsi control three (scntl3) register. 5. set the sclk doubler select bit ( scsi test one (stest1) , bit 2). 6. clear the halt scsi clock bit. register: 0x4e (0xce) scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows all scsi control and data lines to be asserted through the socl and scsi output data latch (sodl) registers regardless of whether the LSI53C875 is con?ured as a target or initiator. note: do not set this bit during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. set this bit if a scsi gross error condition occurs and to clear the offset when a synchronous transfer does not complete successfully. the bit automatically clears itself after resetting the synchronous offset. dif scsi differential mode 5 setting this bit allows the LSI53C875 to interface properly to external differential transceivers. its only real effect is to 3-state the sbsy/, ssel/, and srst/ pads so that they can be used as pure inputs. clearing this bit enables se operation. set this bit in the initialization routine if the differential pair interface is used. 76543210 sce rof dif slb szm aws ext low 00000000
5-74 scsi operating registers slb scsi loopback mode 4 setting this bit allows the LSI53C875 to perform scsi loopback diagnostics. that is, it enables the scsi core to simultaneously perform as both the initiator and the target. szm scsi high impedance mode 3 setting this bit places all the open drain 48 ma scsi drivers into a high impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. aws always wide scsi 2 when this bit is set, all scsi information transfers are done in 16-bit wide mode. this includes data, message, command, status, and reserved phases. normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the scsi speci?ations. ext extend sreq/sack filtering 1 tolerant scsi receiver technology includes a special digital ?ter on the sreq/ and sack/ pins which causes the disregarding of glitches on deasserting edges. setting this bit increases the ?tering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals. never set this bit during fast scsi (greater than 5 mbytes transfers per second) operations, because a valid assertion could be treated as a glitch. this bit does not affect the ?tering period when the ultra enable bit in the scsi control three (scntl3) register is set. when the LSI53C875 is executing ultra scsi transfers, the ?tering period is automatically set at 15 ns. low scsi low level mode 0 setting this bit places the LSI53C875 in low level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in scsi scripts mode. it is not necessary to
5-75 set this bit for access to the scsi bit-level registers scsi output data latch (sodl) , scsi bus control lines (sbcl) , and input registers. register: 0x4f (0xcf) scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of tolerant technology. active negation causes the scsi request, acknowledge, data, and parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C875 is driving these signals. active deassertion of these signals occurs only when the LSI53C875 is in an information transfer phase. when operating in a differential environment or at fast scsi timings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on tolerant technology, refer to chapter 1, ?eneral description. set this bit if the ultra bit in scsi control three (scntl3) is set. str scsi fifo test read 6 setting this bit places the scsi core into a test mode in which the scsi fifo is easily read. reading the least signi?ant byte of the scsi output data latch (sodl) register causes the fifo to unload. the functions are summarized in the table below. 76543210 te str hsc dsi s16 ttm csf stw 00000000 register name register operation fifo bits fifo function sodl read [15:0] unload sodl0 read [7:0] unload sodl1 read [15:8] none
5-76 scsi operating registers hsc halt scsi clock 5 asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit is used for test purposes or to lower i dd during a power-down mode. this bit is used when the scsi clock doubler is operating. for additional information on the clock doubler, see chapter 2, ?unctional description. dsi disable single initiator response 4 if this bit is set, the LSI53C875 ignores all bus-initiated selection attempts that employ the single initiator option from scsi-1. in order to select the LSI53C875 while this bit is set, the LSI53C875s scsi id and the initiators scsi id must both be asserted. assert this bit in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. s16 16-bit system 3 if this bit is set, all devices in the scsi system implementation are assumed to be 16-bit. this causes the LSI53C875 to always check the parity bit for scsi ids [15:8] during bus-initiated selection or reselection, assuming parity checking has been enabled. if an 8-bit scsi device attempts to select the LSI53C875 while this bit is set, the LSI53C875 will ignore the selection attempt. this is because the parity bit for ids [15:8] will be undriven. see the description of the enable parity checking bit in the scsi control zero (scntl0) register for more information. ttm timer test mode 2 asserting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers and if the respective bits in the scsi interrupt enable one (sien1) register are asserted, the LSI53C875 generates interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used. csf clear scsi fifo 1 setting this bit causes the ?ull ?gs for the scsi fifo to be cleared. this empties the fifo. this bit is self-clearing. in addition to the scsi fifo pointers, the
5-77 scsi input data latch (sidl) , scsi output data latch (sodl) , and sodr full bits in the scsi status zero (sstat0) and scsi status two (sstat2) are cleared. stw scsi fifo test write 0 setting this bit places the scsi core into a test mode in which the fifo is easily read or written. while this bit is set, writes to the least signi?ant byte of the scsi output data latch (sodl) register cause the entire word contained in this register to be loaded into the fifo. writing the least signi?ant byte of the scsi output data latch (sodl) register will cause the fifo to load. these functions are summarized in the table below. register: 0x50?x51 (0xd0?xd1) scsi input data latch (sidl) read only sidl scsi input data latch [15:0] this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data received from the scsi bus can be read from this register. data can be written to the scsi output data latch (sodl) register and then read back into the LSI53C875 by reading this register to allow loopback testing. when receiving scsi data, the data ?ws into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; scsi input data latch (sidl) contains latched data and the scsi bus data lines (sbdl) always contains exactly what is currently on the scsi data bus. the power-up value of this register is indeterminate. register name register operation fifo bits fifo function sodl write [15:0] load sodl0 write [7:0] load sodl1 write [15:8] none 15 0 sidl xxxxx x x x x xxx x xxx
5-78 scsi operating registers registers: 0x54?x55 (0xd4?xd5) scsi output data latch (sodl) read/write sodl scsi output data latch [15:0] this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register is used to send data using programmed i/o. data ?ws through this register when sending data in any mode. it is also used to write to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. registers: 0x58?x59 (0xd8?xd9) scsi bus data lines (sbdl) read only sbdl scsi bus data lines [15:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostic testing or in low level mode. if the chip is in wide mode scsi control three (scntl3) , bit 3, scsi test two (stest2) , bit 2 and scsi bus data lines (sbdl) is read, both byte lanes are checked for parity regardless of phase. when in a nondata phase, this will cause a parity error interrupt to be generated because upper byte lane parity is invalid. 15 0 sodl xxxxx x x x x xxx x xxx 15 0 sbdl xxxxx x x x x xxx x xxx
5-79 registers: 0x5c?x5f (0xdc?xdf) scratch register b (scratchb) read/write scratchb scratch register b [31:0] this is a general purpose user de?able scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register will alter its contents. the LSI53C875 cannot fetch scripts instructions from this location. when bit 3 in the chip test two (ctest2) register is set, this register contains the base address for the 4 kbytes internal ram. setting chip test two (ctest2), bit 3 only causes the base address to appear in the scratch reg- ister b (scratchb) register; any information that was previously in the register remains intact. any writes to this register while the bit is set pass through to the actual scratch register b (scratchb) register. the power-up values are indeterminate. registers: 0x60?x7f (0xe0?xff) scratch registers c? (scratchc?cratchj) read/write these registers are general purpose scratch registers for user-de?ed functions. the LSI53C875 cannot fetch scripts instructions from this location. the power-up value of these registers is indeterminate. 31 0 scratchb xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-80 scsi operating registers
LSI53C875/875e pci to ultra scsi i/o processor 6-1 chapter 6 instruction set of the i/o processor after power-up and initialization, the LSI53C875 can be operated in the low level register interface mode or in the high level scsi scripts mode. chapter 6 is divided into the following sections: ? section 6.1, ?csi scripts ? section 6.2, ?lock move instructions ? section 6.3, ?/o instruction ? section 6.4, ?ead/write instructions ? section 6.5, ?ransfer control instructions ? section 6.6, ?emory move instructions ? section 6.7, ?oad and store instructions with the low level register interface mode, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low level dma signals, which allows creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chips pins. 6.1 scsi scripts to operate in the scsi scripts mode, the LSI53C875 requires only a scripts start address. the start address must be at a longword (four byte) boundary. this aligns subsequent scripts at a longword
6-2 instruction set of the i/o processor boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the LSI53C875 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer (dsp) register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the LSI53C875 to make decisions based on the status of the scsi bus, which of?ads the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery should never be required. the following types of scripts instructions are implemented in the LSI53C875 as shown in table 6.1 : table 6.1 scripts instructions instruction description block move block move instruction moves data between the scsi bus and memory. i/o or read/write i/o or read/write instructions cause the LSI53C875 to trigger common scsi hardware sequences, or to move registers. transfer control transfer control instruction allows scripts instructions to make decisions based on real time scsi bus conditions. memory move memory move instruction causes the LSI53C875 to execute block moves between different parts of main memory. load and store load and store instructions provide a more ef?ient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction.
scsi scripts 6-3 each instruction consists of two or three 32-bit words. the ?st 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the ?st two 32-bit opcode fetches is followed by one or two more 32-bit fetch cycles. 6.1.1 sample operation this operation describes execution of a scripts instruction for a block move instruction. ? the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register ?e) the starting address in main memory that points to a scsi scripts program for execution. ? loading the dma scripts pointer (dsp) register causes the LSI53C875 to fetch its ?st instruction at the address just loaded. this will be from main memory or the internal ram, depending on the address. ? the LSI53C875 typically fetches two longwords (64 bits) and decodes the high order byte of the ?st longword as a scripts instruction. if the instruction is a block move, the lower three bytes of the ?st longword are stored and interpreted as the number of bytes to be moved. the second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. ? for a scsi send operation, the LSI53C875 waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the LSI53C875 requests use of the pci bus again to transfer the data. ? when the LSI53C875 is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the pci bus. the LSI53C875 stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process.
6-4 instruction set of the i/o processor the process repeats until the internally stored byte count has reached zero. the LSI53C875 releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer (dsp) register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the LSI53C875 interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the LSI53C875 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or requiring an external dma controller to be programmed. an overview of this process is presented in figure 6.1 . figure 6.1 scripts overview system processor system memory scsi initiator write example select atn 0, alt_addr move from identify_msg_buf, when msg_out move from cmd_buf, when cmd move from data_buf when data_out move from stat_in_buf, when status move from msg_in_buf, when msg_in move scntl2 & 7f to scntl2 clear ack wail disconnect alt2 int 10 ta b l e byte count address byte count address byte count address byte count address message buffer command buffer data buffer status buffer s y s t e m write dsa write dsp fetch scripts data LSI53C875 scsi bus b u s
block move instructions 6-5 6.2 block move instructions performing a block move instruction, bit 5, source i/o - memory enable (siom) and bit 4, destination i/o - memory enable (diom) in the dma mode (dmode) register determines whether the source/destination address resides in memory or i/o space. when data is being moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is being moved off of the scsi bus, diom controls whether that data goes to i/o or memory space. 6.2.1 first dword it[1:0] instruction type-block move [31:30] ia indirect addressing 29 when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chips address register and incremented as data is transferred. the address of the data to be moved is in the second dword of this instruction. when set, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chips dma next address (dnad) register using a third longword fetch (4-byte transfer across the host computer bus). direct the byte count and absolute address are as follows. indirect use the fetched byte count, but fetch the data address from the address in the instruction. command byte count address of data command byte count address of pointer to data
6-6 instruction set of the i/o processor once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows a table of data buffer addresses to be speci?d. using the lsi logic scsi scripts assembler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. this feature makes it possible to locate scsi scripts in a prom. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. table indirect 28 when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch ?st the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. figure 6.2 illustrates the block move instruction register. command not used don? care table offset
block move instructions 6-7 figure 6.2 block move instruction register prior to the start of an i/o, the data structure address (dsa) register should be loaded with the base address of the i/o data structure. the address may be any address on a longword boundary. after a table indirect opcode is fetched, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the LSI53C875. execution of the move begins at this point. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit block move byte counter i/o c/d msg/ opcode table indirect addressing indirect addressing (lsi53c700 family compatible) 0 - instruction type - block move 0 - instruction type - block move
6-8 instruction set of the i/o processor scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: ? the eight bytes of data in the move instruction must be contiguous, as shown below, and ? indirect data fetches are not available during execution of a memory-to-memory dma operation. opcode 27 this 1-bit ?ld de?es the instruction to be executed as a block move (move). target mode these instructions perform the following steps: 1. the LSI53C875 veri?s that it is connected to the scsi bus as a target before executing this instruction. 2. the LSI53C875 asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as de?ed by the phase field bits in the instruction. 3. if the instruction is for the command phase, the LSI53C875 receives the ?st command byte and decodes its scsi group code. if the scsi group code is either group 0, group 1, group 2, or group 5, and if the vendor unique enhancement 1 (vue1) bit ( scsi control two (scntl2), bit 1) is clear, then the LSI53C875 00 byte count physical data address opc instruction de?ed 0move 1 chmov
block move instructions 6-9 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. if the vendor unique enhancement 1 (vue1) bit ( scsi control two (scntl2), bit 1) is set, the LSI53C875 receives the number of bytes in the byte count regardless of the group code. if the vendor unique enhancement 1 bit is clear and group code is vendor unique, the LSI53C875 receives the number of bytes in the count. if any other group code is received, the dma byte counter (dbc) register is not modi?d and the LSI53C875 requests the number of bytes speci?d in the dma byte counter (dbc) register. if the dma byte counter (dbc) register contains 0x000000, an illegal instruction interrupt is generated. 4. the LSI53C875 transfers the number of bytes speci?d in the dma byte counter (dbc) register starting at the address speci?d in the dma next address (dnad) register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C875 stores the last byte in the scsi wide residue (swide) register during a receive operation. this byte is combined with the ?st byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scsi control one (scntl1) register controls whether the LSI53C875 halts on these conditions immediately, or waits until completion of the current move.
6-10 instruction set of the i/o processor initiator mode these instructions perform the following steps: 1. the LSI53C875 veri?s that it is connected to the scsi bus as an initiator before executing this instruction. 2. the LSI53C875 waits for an unserviced phase to occur. an unserviced phase is any phase (with sreq/ asserted) for which the LSI53C875 has not yet transferred data by responding with a sack/. 3. the LSI53C875 compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) register. these phase lines are latched when sreq/ is asserted. 4. if the scsi phase bits match the value stored in the scsi scsi status one (sstat1) register, the LSI53C875 transfers the number of bytes speci?d in the dma byte counter (dbc) register starting at the address pointed to by the dma next address (dnad) register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C875 stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output control latch (socl) register during a send operation. this byte is combined with the ?st byte from the subsequent transfer so that a wide transfer can complete. opc instruction de?ed 0 chmov 1move
block move instructions 6-11 5. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the LSI53C875 generates a phase mismatch interrupt and the instruction is not executed. 6. during a message-out phase, after the LSI53C875 has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the LSI53C875 deasserts satn/ during the ?al sreq/sack/ handshake. 7. when the LSI53C875 is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this 3-bit ?ld de?es the desired scsi information transfer phase. when the LSI53C875 operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the LSI53C875 operates in target mode, the LSI53C875 asserts the phase de?ed in this ?ld. the following table describes the possible combinations and the corresponding scsi phase. tc[23:0] transfer counter [23:0] this 24-bit ?ld speci?s the number of data bytes to be moved between the LSI53C875 and system memory. the ?ld is stored in the dma byte counter (dbc) reg- ister. when the LSI53C875 transfers data to/from mem- ory, the dbc register is decremented by the number of msg c_d i_o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in
6-12 instruction set of the i/o processor bytes transferred. in addition, the dma next address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dbc register has been decremented to zero. at that time, the LSI53C875 fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this ?ld is not used. the byte count is instead fetched from a table pointed to by the data structure address (dsa) register. 6.2.2 second dword start address [31:0] this 32-bit ?ld speci?s the starting address of the data to move to/from memory. this ?ld is copied to the dma next address (dnad) register. when the LSI53C875 transfers data to or from memory, the dnad register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this ?ld is an offset into a table pointed to by the data structure address (dsa) . the table entry contains byte count and address information. 6.3 i/o instruction 6.3.1 first dword it[1:0] instruction type - i/o instruction [31:30] opc[2:0] opcode [29:27] the following opcode bit con?urations have different meanings, depending on whether the LSI53C875 is operating in initiator or target mode. note: opcode selections 101?11 are considered read/write instructions and are described in section 6.4, ?ead/write instructions.
i/o instruction 6-13 target mode reselect instruction the LSI53C875 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the LSI53C875 wins arbitration, it attempts to reselect the scsi device whose id is de?ed in the destination id ?ld of the instruction. once the LSI53C875 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. if the LSI53C875 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. manually set the LSI53C875 to initiator mode if it is reselected, or to tar- get mode if it is selected. disconnect instruction the LSI53C875 disconnects from the scsi bus by deasserting all scsi signal outputs. wait select instruction if the LSI53C875 is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. opc2 opc1 opc0 instruction de?ed 0 0 0 reselect 0 0 1 disconnect 0 1 0 wait select 011 set 1 0 0 clear
6-14 instruction set of the i/o processor if reselected, the LSI53C875 fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. manually set the LSI53C875 to initiator mode when it is reselected. if the cpu sets the sigp bit in the interrupt status (istat) register, the LSI53C875 aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in the target mode. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output con- trol latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode. figure 6.3 illustrates the i/o instruction register.
i/o instruction 6-15 figure 6.3 i/o instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register r rr r set/clear atn/ set/clear ack/ set/clear target mode set/clear carry encoded destination id 0 encoded destination id 1 encoded destination id 2 encoded destination id 3 reserved reserved reserved reserved select with atn/ table indirect mode relative address mode opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - i/o 0 - instruction type - i/o second 32-bit word of the i/o instruction 32-bit jump address
6-16 instruction set of the i/o processor initiator mode select instruction the LSI53C875 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the LSI53C875 wins arbitration, it attempts to select the scsi device whose id is de?ed in the destination id ?ld of the instruction. once the LSI53C875 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection completes. it continues executing scripts until a script that requires a response from the target is encountered. if the LSI53C875 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. manually set the LSI53C875 to initiator mode if it is reselected, or to tar- get mode if it is selected. if the select with satn/ ?ld is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the LSI53C875 waits for the target to perform a ?egal disconnect from the scsi bus. a ?egal disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the LSI53C875 receives a disconnect message or a command complete message. opc2 opc1 opc0 instruction de?ed 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 0 1 1 set 1 0 0 clear
i/o instruction 6-17 wait reselect instruction if the LSI53C875 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. manually set the lsi53c825a to target mode when it is selected. if the LSI53C875 is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if the cpu sets the sigp bit in the interrupt status (istat) register, the LSI53C875 aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?ld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output con- trol latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next address (dnad) register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the
6-18 instruction set of the i/o processor data structure address (dsa) register, and used as an offset relative to the value in the data structure address (dsa) register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data structure address (dsa) with the base address of the i/o data structure. any address on a longword boundary is allowed. after a table indirect opcode is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: ? the i/o data structure must lie within the 8 mbytes above or below the base address. ? an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the con?uration bits are ordered as in the scsi control three (scntl3) register. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. use bits 25 and 26 individually or in combination to produce the following conditions: con? id offset/period 00 bit 25 bit 26 addressing mode 0 0 direct 0 1 table indirect 1 0 relative 1 1 table relative
i/o instruction 6-19 direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. the value in bits [23:0] of the ?st four bytes of the scripts is added to the data structure base address to form the fetch address. sel select with atn/ 24 this bit speci?s whether satn/ is asserted during the selection phase when the LSI53C875 is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset command table offset alternate jump offset
6-20 instruction set of the i/o processor r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit ?ld speci?s the destination scsi id for an i/o instruction. r reserved [15:11] cc set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. clear- ing this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction con?ures the LSI53C875 as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction con?ures the LSI53C875 as an initiator device (this clears bit 0 of the scntl0 register). r reserved [8:7] ack set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal. setting either of these bits will set or reset the corresponding bit in the scsi output control latch (socl) register, depending on the instruction used. the set instruction is used to assert sack/ and/or satn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus unless the LSI53C875 is operating as an initiator or the scsi loopback enable bit is set in the scsi status two (sstat2) register.
read/write instructions 6-21 the set/clear scsi ack/atn instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, is issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 6.3.2 second dword sa start address [31:0] this 32-bit ?ld contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 6.4 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the speci?d register and the scsi first byte received (sfbr) register, then stores the result back to the speci?d register or the sfbr. 6.4.1 first dword it[1:0] instruction type - read/write instruction [31:30] the read/write instruction uses operator bits 26 through 24 in conjunction with the opcode bits to determine which instruction is currently selected. opc[2:0] opcode [29:27] the combinations of these bits determine if the instruction is a read/write or an i/o instruction. opcodes 000 through 100 are considered i/o instructions.
6-22 instruction set of the i/o processor o[2:0] operator [26:24] these bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to table 6.1 for ?ld de?itions. d8 use data8/sfbr 23 when this bit is set, sfbr is used instead of the data8 value during a read-modify-write instruction (see table 6.1 ). this allows the user to add two register values. a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from sfbr cycles. a[6:0] selects an 8-bit source/destination register within the LSI53C875. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. r reserved [7:0] 6.4.2 second dword destination address [31:0] this ?ld contains the 32-bit destination address where the data to move. 6.4.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. subtraction is not available when sfbr is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, ?st xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2s complement of the subtrahend. the two values are then added to obtain the difference.
read/write instructions 6-23 figure 6.4 illustrates the read/write instruction register. figure 6.4 read/write instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 use data8/sfbr operator 0 operator 1 operator 2 opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - r/w 0 - instruction type - r/w immediate data reserved (must be 0) register address
6-24 instruction set of the i/o processor 6.4.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the sfbr. table 6.2 shows the possible read-modify-write operations. the possible functions of this instruction are: ? write one byte (value contained within the scripts instruction) into any chip register. ? move to/from the sfbr from/to any other register. ? alter the value of a register with and, or, add, xor, shift left, or shift right operators. ? after moving values to the sfbr, the compare and jump, call, or similar instructions are used to check the value. ? a move-to-sfbr followed by a move-from-sfbr is used to perform a register-to-register move. table 6.2 read/write instructions operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr 000 move data into register. syntax: ?ove data8 to rega move data into scsi first byte received (sfbr) register. syntax: ?ove data8 to sfbr move data into register. syntax: ?ove data8 to rega 001 1 shift register one bit to the left and place the result in the same register. syntax: ?ove rega shl rega shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega shl sfbr shift the scsi first byte received (sfbr) register one bit to the left and place the result in the register. syntax: ?ove sfbr shl rega 010 or data with register and place the result in the same register. syntax: ?ove rega | data8 to rega or data with register and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega | data8 to sfbr or data with sfbr and place the result in the register. syntax: ?ove sfbr | data8 to rega 011 xor data with register and place the result in the same register. syntax: ?ove rega xor data8 to rega xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega xor data8 to sfbr xor data with sfbr and place the result in the register. syntax: ?ove sfbr xor data8 to rega
read/write instructions 6-25 miscellaneous notes: ? substitute the desired register name or address for ?ega in the syntax examples. ? data8 indicates eight bits of data. ? use scsi first byte received (sfbr) instead of data8 to add two register values. 100 and data with register and place the result in the same register. syntax: ?ove rega & data8 to rega and data with register and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega & data8 to sfbr and data with sfbr and place the result in the register. syntax: ?ove sfbr & data8 to rega 101 1 shift register one bit to the right and place the result in the same register. syntax: ?ove rega shr rega shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega shr sfbr shift the scsi first byte received (sfbr) register one bit to the right and place the result in the register. syntax: ?ove sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: ?ove rega + data8 to rega add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: ?ove sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: ?ove rega + data8 to rega with carry add data to register with carry and place the result in the scsi first byte received (sfbr) register. syntax: ?ove rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: ?ove sfbr + data8 to rega with carry 1. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 6.2 read/write instructions (cont.) operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr
6-26 instruction set of the i/o processor 6.5 transfer control instructions 6.5.1 first dword it[1:0] instruction type - transfer control instruction [31:30] opc[2:0] opcode [29:27] this 3-bit ?ld speci?s the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase ?ld, and/or a comparison of the first byte received with the data compare ?ld. each instruction can operate in initiator or target mode. jump instruction the LSI53C875 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ed by the phase compare, data compare and true/false bit ?lds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. the dsp register now contains the address of the next instruction. if the comparisons are false, the LSI53C875 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. opc2 opc1 opc0 instruction de?ed 000jump 0 0 1 call 0 1 0 return 0 1 1 interrupt 1 x x reserved
transfer control instructions 6-27 call instruction the LSI53C875 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ed by the phase compare, data compare, and true/false bit ?lds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the LSI53C875 executes a call instruction, the instruction pointer contained in the dma scripts pointer (dsp) register is stored in the temp register. since the temporary (temp) register is not a stack and can only hold one longword, nested call instructions are not allowed. if the comparisons are false, the LSI53C875 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?d. figure 6.5 illustrates the transfer control instruction.
6-28 instruction set of the i/o processor figure 6.5 transfer control instructions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register wait for valid phase compare phase compare data jump if: true=1, false=0 interrupt on the fly carry test 0 (reserved) relative addressing mode i/o c/d msg opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - transfer control 0 - instruction type - transfer control mask for compare data to be compared with the scsi first byte received
transfer control instructions 6-29 return instruction the LSI53C875 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ed by the phase compare, data compare, and true/false bit ?lds. if the comparisons are true, then it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction. when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dma scripts pointer (dsp) register. the LSI53C875 does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, then the LSI53C875 fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modi?d. interrupt instruction the LSI53C875 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ed by the phase compare, data compare, and true/false bit ?lds. if the comparisons are true, then the LSI53C875 generates an interrupt by asserting the irq/ signal. the 32-bit address ?ld stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the interrupt service routine to quickly identify the point at which the interrupt occurred. the LSI53C875 halts and the dma scripts pointer (dsp) register must be written to start any further operation. interrupt-on-the-fly instruction the LSI53C875 can do a true/false comparison of the alu carry bit or compare the phase and/or data as de?ed by the phase compare, data compare, and
6-30 instruction set of the i/o processor true/false bit ?lds. if the comparisons are true, and the interrupt-on-the-fly bit is set (bit 2), the LSI53C875 asserts the interrupt-on-the-fly bit. scsip[2:0] scsi phase [26:24] this 3-bit ?ld corresponds to the three scsi bus phase signals that are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible combinations and their corresponding scsi phase. these bits are only valid when the LSI53C875 is operating in initiator mode. clear these bits when the LSI53C875 is operating in the target mode. ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address (which is pointing to the next instruction, not the one currently executing). the relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. msg c/d i/o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in command condition codes absolute alternate address
transfer control instructions 6-31 the scripts program counter is a 32-bit value pointing to the script currently being executed by the LSI53C875. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2s complement), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and could be stored in and executed from a prom. ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit ( interrupt status (istat) , bit 2) is asserted. jmp jump if true/false 19 this bit determines whether the LSI53C875 branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition. command condition codes don? care alternate jump offset
6-32 instruction set of the i/o processor cd compare data 18 when this bit is set, the ?st byte received from the scsi data bus (contained in scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the LSI53C875 is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the LSI53C875 is operating in target mode and this bit is set, it tests for an active scsi satn/ signal. wvp wait for valid phase 16 if the wait for valid phase bit is set, the LSI53C875 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the LSI53C875 compares the scsi phase and data immediately. dcm data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 01111111b and data compare value of 1xxxxxxxb allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. bit 19 result of compare action 0 false jump taken 0 true no jump 1 false no jump 1 true jump taken
memory move instructions 6-33 dcv data compare value [7:0] this 8-bit ?ld is the data to be compared against the register. these bits are used in conjunction with the data compare mask field to test for a particular data value. 6.5.2 second dword jump address [31:0] this 32-bit ?ld contains the address of the next instruction to fetch when a jump is taken. once the LSI53C875 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 6.6 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the speci?d number of bytes from the source address to the destination address. allowing the LSI53C875 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions: ? both the source and destination addresses must start with the same address alignment a[1:0]. if the source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. ? indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another scripts is fetched from system memory.
6-34 instruction set of the i/o processor the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved. it[2:0] instruction type - memory move [31:39] r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the LSI53C875 performs a memory move without ?shing the prefetch unit. when this bit is clear, the memory move instruction automatically ?shes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, ?unc- tional description. tc[23:0] transfer count [23:0] the number of bytes to be transferred is stored in the lower 24 bits of the ?st instruction word. 6.6.1 read/write system memory from scripts by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the LSI53C875 responds to addresses as de?ed in the base address zero (i/o) or base address one (memory) registers, it can be accessed during a memory move operation if the source or destination address decodes to within the chips register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. in this way, register values are saved to system memory and later restored, and scripts can make decisions based on data values in system memory.
memory move instructions 6-35 the sfbr is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, ?st move the byte to an intermediate LSI53C875 register (for example, a scratch register), and then to the sfbr. the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. 6.6.2 second dword dsps register [31:0] these bits contain the source address of the memory move. 6.6.3 third dword temp register [31:0] these bits contain the destination address for the memory move. figure 6.6 illustrates the memory move instruction.
6-36 instruction set of the i/o processor figure 6.6 memory move instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit memory move byte counter no flush 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 - instruction type - memory move 1 - instruction type - memory move 1 - instruction type - memory move 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 temp register
load and store instructions 6-37 6.7 load and store instructions the load and store instructions provide a more ef?ient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two dword opcodes. the ?st dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load or store, or the offset from the data structure address (dsa) , depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the destination memory address in the store instruction and the source memory address of the load instruction may not map back to the operating register set of the chip. this excludes the scripts ram and rom memory spaces. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load and store utilizes the pci commands for i/o read and i/o write to access the i/o space. bit a1 bit a0 number of bytes allowed to load and store 0 0 one, two, three or four 0 1 one, two, or three 1 0 one or two 1 1 one
6-38 instruction set of the i/o processor 6.7.1 first dword it[2:0] instruction type [31:29] these bits should be 111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address used to perform the load and store to/from. when this bit is set, the chip determines the memory address to per- form the load and store to/from by adding the 24-bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa) . r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the LSI53C875 performs a store without ?shing the prefetch unit. when this bit is cleared, the store instruction automatically ?shes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit has no effect on the load instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, ?unc- tional description. ls load/store 24 when this bit is set, the instruction is a load. when cleared, it is a store. bit source destination siom (load) memory register diom (store) register memory
load and store instructions 6-39 r reserved 23 ra[6:0] register address [22:16] a[6:0] selects the register to load and store to/from within the LSI53C875. note: it is not possible to load the scsi first byte received (sfbr) register, although it is possible to store the sfbr contents to another location. r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load and store. 6.7.2 second dword memory/io address/dsa offset [31:0] this is the actual memory location of where to load and store, or the offset from the data structure address (dsa) register value. figure 6.7 illustrates the load and store instruction format.
6-40 instruction set of the i/o processor figure 6.7 load and store instruction format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register - memory/ i/o address/dsa offset dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 0 (reserved) load/store no flush 0 - reserved 0 - reserved dsa relative 1 1 1 register address instruction type - load and store reserved (must be 0) byte count (number of bytes to load/store)
LSI53C875/875e pci to ultra scsi i/o processor 7-1 chapter 7 instruction set of the i/o processor this chapter speci?s the LSI53C875 electrical and mechanical characteristics. it is divided into the following sections: ? section 7.1, ?c characteristics ? section 7.2, ?olerant technology electrical characteristics ? section 7.3, ?c characteristics ? section 7.4, ?ci and external memory interface timing diagrams ? section 7.5, ?ci and external memory interface timing ? section 7.6, ?csi timing diagrams ? section 7.7, ?ackage drawings 7.1 dc characteristics this section describes the LSI53C875 dc characteristics. table 7.1 through table 7.14 give current and voltage speci?ations. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied.
7-2 instruction set of the i/o processor table 7.1 absolute maximum stress ratings symbol parameter min max unit test conditions t stg storage temperature ? 55 150 c v dd supply voltage ? 0.5 7.0 v v in input voltage v ss ? 0.5 v dd +0.5 v i lp 1 1. ? 2v dc characteristics 7-3 table 7.3 scsi signals?d[15:0]/, sdp[1:0]/, sreq/, sack/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh 1 1. tolerant active negation enabled. output high voltage 2.5 3.5 v 2.5 ma v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage ? 10 10 a table 7.4 scsi signals?msg, si_o/, sc_d/, satn/, sbsy/, ssel/, srst/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage (srst/ only) ? 10 ? 500 10 ? 50 a table 7.5 input signals?lk, sclk, gnt/, idsel, rst/, testin, diffsens, big_lit/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v i in input leakage ? 10 10 a note: sclk and big_lit/ have 100 a pull-ups, and gnt/ and idsel have 25 a pull-ups, that are enabled when testin is low. testin has a 100 a pull-up that is always enabled.
7-4 instruction set of the i/o processor table 7.6 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads 7 pf c io input capacitance of i/o pads 10 pf table 7.7 output signals?ac/_testout, req/ symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v ? 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage ? 10 10 a note: req/ has a 100 a pull-up that is enabled when testin is low. table 7.8 output signals?rq/, sdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/, mwe/ symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v ? 4ma 1 1. for irq/, test conditions are 8 ma. note: irq/, mas/[1:0], mce/, moe/, and mwe/ have a 100 a pull-up that is enabled when testin is low. irq/ can be enabled with a register as an open drain with an internal 100 a pull-up. v ol output low voltage v ss 0.4 v 4 ma 1 i oz 3-state leakage ? 10 10 a table 7.9 output signal?err/ symbol parameter min max unit test conditions v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage ? 10 10 a
dc characteristics 7-5 table 7.10 bidirectional signals?d[31:0], c_be[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage 2.4 v dd v16ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage ? 10 10 a note: all the signals in this table have 25 a pull-ups that are enabled when testin is low. table 7.11 bidirectional signals?pio0_fetch/, gpio1_master/, gpio2_mas2/, gpio3, gpio4 symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage 2.4 v dd v ? 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage ? 10 10 a note: all the signals in this table have 100 a pull-ups that are enabled when testin is low.
7-6 instruction set of the i/o processor table 7.12 bidirectional signals?ad[7:0] symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v ih input high voltage - external memory pull-downs 3.85 v dd +0.5 v v il input low voltage v ss ? 0.5 0.8 v v il input low voltage - external memory pull-downs v ss ? 0.5 1.35 v v oh output high voltage 2.4 v dd v ? 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage ? 10 10 a note: all the signals in this table have 100 a pull-ups that are enabled when testin is low. table 7.13 input signals?di, tms, tck (LSI53C875j, LSI53C875jb, LSI53C875n only) symbol parameter min max unit test conditions v ih input high voltage 3.85 v dd +0.5 v v il input low voltage v ss ? 0.5 1.35 v i in input leakage ? 800 ? 200 a table 7.14 output signal?do (LSI53C875, LSI53C875jb, LSI53C875n only) symbol parameter min max unit test conditions v oh output high voltage v dd ? 0.5 v dd v ? 4ma v ol output low voltage v ss 0.5 v 4 ma i oz 3-state leakage ? 10 10 a
tolerant technology electrical characteristics 7-7 7.2 tolerant technology electrical characteristics the LSI53C875 features tolerant technology, which includes active negation on the scsi drivers and input signal ?tering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 7.15 provides electrical characteristics for se scsi signals. figure 7.1 through figure 7.5 provide reference information for testing scsi signals. table 7.15 tolerant technology electrical characteristics symbol parameter min max unit test conditions v oh 1 output high voltage 2.5 3.5 v i oh = 2.5 ma v ol output low voltage 0.1 0.5 v i ol =48ma v ih input high voltage 2.0 7.0 v v il input low voltage ? 0.5 0.8 v referenced to v ss v ik input clamp voltage ? 0.66 ? 0.77 v v dd = 4.75; i i = ? 20 ma v th threshold, high to low 1.1 1.3 v v tl threshold, low to high 1.5 1.7 v v th ? tl hysteresis 200 400 mv i oh 1 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 1 short-circuit output high current 625 ma output driving low, pin shorted to v dd supply 2 i osl short-circuit output low current 95 ma output driving high, pin shorted to v ss supply i lh input high leakage 10 a ? 0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage ? 10 a ? 0.5 < v dd < 5.25 v pin = 0.5 v r i input resistance 20 m ? scsi pins 3 c p capacitance per pin 10 pf pqfp t r 1 rise time, 10% to 90% 9.7 18.5 ns figure 7.1 t f fall time, 90% to 10% 5.2 14.7 ns figure 7.1 dv h /dt slew rate, low to high 0.15 0.49 v/ns figure 7.1 dv l /dt slew rate, high to low 0.19 0.67 v/ns figure 7.1
7-8 instruction set of the i/o processor figure 7.1 rise and fall time test conditions figure 7.2 scsi input filtering esd electrostatic discharge 2 kv mil-std-883c; 3015-7 latch-up 100 ma filter delay 20 30 ns figure 7.2 extended ?ter delay 40 60 ns figure 7.2 1. active negation outputs only: data, parity, sreq/, sack/. 2. single pin only; irreversible damage may occur if sustained for one second. 3. scsi reset pin has 10 k ? pull-up resistor. note: these values are guaranteed by periodic characterization; they are not 100% tested on every device. table 7.15 tolerant technology electrical characteristics symbol parameter min max unit test conditions 2.5 v 47 ? 20 pf + ? req/ or ack/ input t 1 v th note: t 1 is the input ?tering period.
tolerant technology electrical characteristics 7-9 figure 7.3 hysteresis of scsi receiver figure 7.4 input current as a function of input voltage 1 receiving logic level 0 1.1 1.3 1.5 1.7 input voltage (volts) +40 +20 0 ? 20 ? 40 ? 4 0 4 8 12 16 ? 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v
7-10 instruction set of the i/o processor figure 7.5 output current as function of output voltage 7.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to section 7.1, ?c characteristics ). chip timings are based on simulation at worst case voltage, temperature, and processing. timings were developed with a load capacitance of 50 pf. table 7.16 and figure 7.6 provide external clock timing data. output sink current (milliamperes) ? 800 ? 600 ? 400 ? 200 0 012345 output voltage (volts) output source current (milliamperes) 20 40 60 80 100 012345 output voltage (volts) 0
ac characteristics 7-11 figure 7.6 clock waveforms table 7.16 clock timing symbol parameter min max unit t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 1 1. this parameter must be met to ensure scsi timings are within speci?ation. 12.5 60 ns t 2 clk low time 2 2. duty cycle not to exceed 60/40. 12 ns sclk low time 2 5ns t 3 clk high time 2 12 ns sclk high time 2 5ns t 4 clk slew rate 1 v/ns sclk slew rate 1 v/ns clk, sclk t 1 t 3 t 4 t 2
7-12 instruction set of the i/o processor table 7.17 and figure 7.7 provide reset input timing data. figure 7.7 reset input table 7.17 reset input symbol parameter min max unit t 1 reset pulse width 10 t clk t 2 reset deasserted setup to clk high 0 ns t 3 mad setup time to clk high (for con?uring the mad bus only) 20 ns t 4 mad hold time from clk high (for con?uring the mad bus only) 20 ns t 2 1. when enabled. clk rst/ mad 1 valid data t 3 t 4 t 1
pci and external memory interface timing diagrams 7-13 table 7.18 and figure 7.8 provide interrupt output timing data. figure 7.8 interrupt output 7.4 pci and external memory interface timing diagrams figure 7.9 through figure 7.30 represent signal activity when the LSI53C875 accesses the pci bus. the timings for the pci and external memory buses are listed on page 7-50 . this section includes timing diagrams for access to three groups of external memory con?urations. the ?st group applies to systems with memory size of 64 kbytes and above; one byte read or write cycle, and fast or normal roms. the second group applies to systems with memory size of 64 kbytes and above, one byte read or write cycles, and slow roms. the third group applies to systems with memory size of 64 kbytes or less, one byte read or write cycles, and normal or fast rom. note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. table 7.18 interrupt output symbol parameter min max unit t 1 clk high to irq/ low 20 ns t 2 clk high to irq/ high 40 ns t 3 irq/ deassertion time 3 clk clk irq/ t 3 t 1 t 2
7-14 instruction set of the i/o processor timing diagrams included in this section are: ? target timing pci con?uration register read pci con?uration register write operating register/scripts ram read operating register/scripts ram write external memory read external memory write ? initiator timing opcode fetch, nonburst burst opcode fetch back-to-back read back-to-back write burst read burst write ? external memory timing read cycle, normal/fast memory ( 64 kbytes), single byte access write cycle, normal/fast memory ( 64 kbytes), single byte access read cycle, normal/fast memory ( 64 kbyte), multiple byte access write cycle, normal/fast memory ( 64 kbyte), multiple byte access read cycle, slow memory ( 64 kbyte) write cycle, slow memory ( 64 kbyte) read cycle, normal/fast memory ( 64 kbyte) write cycle, normal/fast memory ( 64 kbyte) read cycle, slow memory ( 64 kbyte) write cycle, slow memory ( 64 kbyte)
pci and external memory interface timing diagrams 7-15 7.4.1 target timing figure 7.9 through figure 7.14 describe target timing. figure 7.9 pci con?uration register read data out byte enable addr in t 2 in out t 1 t 2 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by system) ad/ (driven by master-addr; LSI53C875-data) c_be/ (driven by master) pa r (driven by master-addr; LSI53C875-data) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) idsel (driven by master) cmd
7-16 instruction set of the i/o processor figure 7.10 pci con?uration register write data in byte enable addr in t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) idsel (driven by master) t 1 t 2 cmd
pci and external memory interface timing diagrams 7-17 figure 7.11 operating register/scripts ram read data byte enable addr in t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) out t 3 in out t 3 LSI53C875-data) LSI53C875-data cmd t 3
7-18 instruction set of the i/o processor figure 7.12 operating register/scripts ram write byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) t 2 data in t 1 t 2 t 1 t 3
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7-20 instruction set of the i/o processor figure 7.13 external memory read t 12 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) data driven by memory) 123456 78910 LSI53C875-data) LSI53C875-data) mad (addr drvn by LSI53C875; high order address middle order address low order address mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) t 1 cmd t 3 t 11 t 15 t 2 t 1 t 2 addr in t 1 t 2 t 1 t 2 t 1 t 13 byte enable gpio_mas2/ (driven by LSI53C875)
pci and external memory interface timing diagrams 7-21 figure 7.13 external memory read (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) data driven by memory) LSI53C875-data) LSI53C875-data) mad (addr drvn by LSI53C875; mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) gpio_mas2/ (driven by LSI53C875) 11 12 13 14 15 16 17 18 19 20 data out t 3 t 2 t 2 21 t 3 out data in t 19 t 17 t 3 t 3 t 14 t 15 t 16
7-22 instruction set of the i/o processor figure 7.14 external memory write clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) 12 3 4 5 6 78 910 LSI53C875-data) byte enable LSI53C875-data) mad (driven by LSI53C875) high order address middle order address low order address gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) t 1 t 2 in t 1 t 2 t 1 t 3 t 11 data in t 23 t 20 t 1 addr in t 1 t 1 t 2 cmd t 12 t 13 mas0/ (driven by LSI53C875)
pci and external memory interface timing diagrams 7-23 figure 7.14 external memory write (cont.) 11 12 13 14 15 16 17 18 19 20 t 2 t 2 21 t 1 t 3 t 3 data in byte enable in data out t 20 t 23 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) LSI53C875-data) LSI53C875-data) mad (driven by LSI53C875) gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) mas0/ (driven by LSI53C875) t 2 t 2 t 22 t 21 t 26 t 24 t 25
7-24 instruction set of the i/o processor 7.4.2 initiator timing figure 7.17 through figure 7.20 describe LSI53C875 initiator timing. figure 7.15 opcode fetch, nonburst t 1 t 7 addr out be clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by system) (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ target-data) (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875-addr; target-data) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by t 9 t 10 t 6 t 4 t 5 t 3 data in addr out data in cmd be cmd t 3 t 1 t 3 t 3 t 1 t 3 t 2 t 2 t 2 t 1 LSI53C875-addr; t 8
pci and external memory interface timing diagrams 7-25 figure 7.16 burst opcode fetch clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by system) (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ target-data) (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875-addr; target-data) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by t 6 t 5 t 3 data in cmd t 3 t 3 t 3 t 1 t 2 t 2 t 2 t 1 LSI53C875-addr; t 8 t 10 t 9 t 7 t 4 addr out t 1 t 2 be out in in t 1 t 3
7-26 instruction set of the i/o processor figure 7.17 back-to-back read t 1 clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by system) (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ target-data) (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875-addr; target-data) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by t 9 t 10 t 6 t 4 t 5 t 3 data in t 3 t 1 t 3 t 1 t 3 t 2 t 2 t 2 t 1 LSI53C875-addr; addr out data in addr out t 2 cmd be cmd be out in out in
pci and external memory interface timing diagrams 7-27 figure 7.18 back-to-back write addr out clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by system) (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by LSI53C875) t 9 t 10 t 6 t 4 t 5 t 3 cmd t 3 t 3 t 3 t 3 t 2 t 2 t 1 data out addr out data out be cmd be t 3 t 3 t 3 t 1 t 2
7-28 instruction set of the i/o processor figure 7.19 burst read 123456 789 t 9 clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by LSI53C875- t 10 t 6 t 3 t 4 t 5 addr out addr out t 2 t 3 data in be cmd t 3 t 3 cmd out in t 2 t 1 t 3 t 3 t 2 t 1 t 3 for address, by target for data) addr, target-data
pci and external memory interface timing diagrams 7-29 figure 7.19 burst read (cont.) 10 11 12 13 14 15 16 17 18 clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by LSI53C875- addr out be cmd out in t 2 t 1 for address, by target for data) addr, target-data 18 19 be in in
7-30 instruction set of the i/o processor figure 7.20 burst write t 3 t 3 123456 789 t 9 clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by LSI53C875) t 10 t 6 t 3 t 4 t 5 t 3 cmd t 3 cmd t 3 (driven by system) addr out data out addr out data out be be t 3 t 3 t 1 t 1 t 3
pci and external memory interface timing diagrams 7-31 figure 7.20 burst write (cont.) 10 11 12 13 14 15 16 17 18 clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ (driven by LSI53C875) (driven by LSI53C875) (driven by LSI53C875) (driven by arbiter) (driven by LSI53C875) ad/ (driven by LSI53C875) irdy/ (driven by target) (driven by LSI53C875) trdy/ stop/ devsel/ (driven by LSI53C875) (driven by target) (driven by target) (driven by LSI53C875) (driven by system) addr out data out t 2 data out be cmd t 2
7-32 instruction set of the i/o processor 7.4.3 external memory timing figure 7.21 through figure 7.30 describe LSI53C875 external memory timing. figure 7.21 read cycle, normal/fast memory ( 64 kbytes), single byte access clk mad (addr driven by LSI53C875; data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) 123456 789 high order address middle order address low order address mas0/ (driven by LSI53C875) t 11 t 12 t 13 t 15f t 14f t 13f
pci and external memory interface timing diagrams 7-33 figure 7.21 read cycle, normal/fast memory ( 64 kbytes), single byte access (cont.) t 17 clk mad (addr driven by LSI53C875 ; data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) 10 11 12 13 14 15 16 17 18 mas0/ (driven by LSI53C875) t 15f t 14f t 16f 19 valid read data t 18 t 19
7-34 instruction set of the i/o processor figure 7.22 write cycle, normal/fast memory ( 64 kbytes), single byte access clk mad (driven by LSI53C875) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) 123456 789 high order address middle order address low order address mas0/ (driven by LSI53C875) t 11 t 12 t 13 t 24 valid write data t 25 t 20 t 23
pci and external memory interface timing diagrams 7-35 figure 7.22 write cycle, normal/fast memory ( 64 kbytes), single byte access (cont.) t 23 clk mad (driven by LSI53C875) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) mwe/ (driven by LSI53C875) 10 11 12 13 14 15 16 17 18 mas0/ (driven by LSI53C875) t 24f valid write data t 25 t 20 19 t 26 t 21 t 22f
7-36 instruction set of the i/o processor figure 7.23 read cycle, normal/fast memory ( 64 kbyte), multiple byte access 12 3456 789101112131415 16 clk (driven by system) frame/ (driven by master) ad (driven by master-addr; c_be/ (driven by master) LSI53C875-data) pa r (driven by master-addr; LSI53C875-data) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) mad (addr driven by LSI53C875) data driven by memory) gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) gpio2_mas0/ (driven by LSI53C875) moe/ (driven by LSI53C875) mce/ (driven by LSI53C875) mwe/ (driven by LSI53C875) in addr cmd in byte enable high order address middle order address low order address
pci and external memory interface timing diagrams 7-37 figure 7.23 read cycle, normal/fast memory ( 64 kbyte), multiple byte access (cont.) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 clk (driven by system) frame/ (driven by master) ad (driven by master-addr; c_be/ (driven by master) LSI53C875-data) pa r (driven by master-addr; LSI53C875-data) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) mad (addr driven by LSI53C875) data driven by memory) gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) moe/ (driven by LSI53C875) mce/ (driven by LSI53C875) mwe/ (driven by LSI53C875) out byte enable low order address data in 33 out data data in
7-38 instruction set of the i/o processor figure 7.24 write cycle, normal/fast memory ( 64 kbyte), multiple byte access 12 3456 789101112131415 16 clk (driven by system) frame/ (driven by master) ad (driven by master-addr; c_be/ (driven by master) LSI53C875-data) pa r (driven by master-addr; LSI53C875-data) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) mad (driven by LSI53C875) gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) moe/ (driven by LSI53C875) mce/ (driven by LSI53C875) mwe/ (driven by LSI53C875) in addr cmd in byte enable high order address middle order address low order address data in data out
pci and external memory interface timing diagrams 7-39 figure 7.24 write cycle, normal/fast memory ( 64 kbyte), multiple byte access (cont.) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 clk (driven by system) frame/ (driven by master) ad (driven by master-addr; c_be/ (driven by master) LSI53C875-data) pa r (driven by master-addr; LSI53C875-data) irdy/ (driven by master) trdy/ (driven by LSI53C875) stop/ (driven by LSI53C875) devsel/ (driven by LSI53C875) mad (driven by LSI53C875) gpio2_mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) moe/ (driven by LSI53C875) mce/ (driven by LSI53C875) mwe/ (driven by LSI53C875) in low order address data out 33 data in byte enable
7-40 instruction set of the i/o processor figure 7.25 read cycle, slow memory ( 64 kbyte) mad (address driven by LSI53C875 data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk middle 1234 56789 mwe/ (driven by LSI53C875) 10 high order address address low order address t 12 t 11 t 13 t 15s t 14s t 16s
pci and external memory interface timing diagrams 7-41 figure 7.25 read cycle, slow memory ( 64 kbyte) (cont.) mad (address driven by LSI53C875 data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven byLSI53C875) moe/ (driven by LSI53C875) clk 11 12 13 14 15 16 17 18 19 mwe/ (driven by LSI53C875) 20 t 13 t 15s t 16s read data valid t 17 t 19 t 18 t 14s
7-42 instruction set of the i/o processor figure 7.26 write cycle, slow memory ( 64 kbyte) mad (driven by LSI53C875) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk middle address 12345678 9 mwe/ (driven by LSI53C875) high order address low order address t 12 t 11 t 13 t 24s t 25 t 20 t 23 valid write data
pci and external memory interface timing diagrams 7-43 figure 7.26 write cycle, slow memory ( 64 kbyte) (cont.) mad (driven by LSI53C875) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk 10 11 12 13 14 15 16 17 18 mwe/ (driven by LSI53C875) t 24s t 25 t 20 t 23 19 t 22s t 26 t 21 valid write data
7-44 instruction set of the i/o processor figure 7.27 read cycle, normal/fast memory ( 64 kbyte) t 19 t 17 mad high order t 11 data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk mwe/ (driven by LSI53C875) (addr driven by LSI53C875; address low order address valid write data t 12 t 13 t 15f t 14f t 16f t 18
pci and external memory interface timing diagrams 7-45 figure 7.28 write cycle, normal/fast memory ( 64 kbyte) mad high order mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk mwe/ (driven by LSI53C875) address low order address t 12 t 13 t 24f t 25 t 26 (driven by LSI53C875) t 11 valid write data t 20 t 23 t 21 t 22f
7-46 instruction set of the i/o processor figure 7.29 read cycle, slow memory ( 64 kbyte) mad (address driven by LSI53C875 data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk 1234 5678 9 mwe/ (driven by LSI53C875) 10 high order low order address t 12 t 11 address t 13 t 15s t 14s t 16s
pci and external memory interface timing diagrams 7-47 figure 7.29 read cycle, slow memory ( 64 kbyte) (cont.) mad (address driven by LSI53C875 data driven by memory) mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk 11 12 13 14 15 16 17 18 19 mwe/ (driven by LSI53C875) 20 valid read data t 15s t 14s t 16s t 18 t 17 t 19
7-48 instruction set of the i/o processor figure 7.30 write cycle, slow memory ( 64 kbyte) mad mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk 1234 5678 9 mwe/ (driven by LSI53C875) high order low order address t 12 t 11 address t 13 t 24s t 25 (driven by LSI53C875) valid write data t 20 t 23
pci and external memory interface timing diagrams 7-49 figure 7.30 write cycle, slow memory ( 64 kbyte) (cont.) mad mas2/ (driven by LSI53C875) mas1/ (driven by LSI53C875) mas0/ (driven by LSI53C875) mce/ (driven by LSI53C875) moe/ (driven by LSI53C875) clk 10 11 12 13 14 15 16 17 18 mwe/ (driven by LSI53C875) t 24s t 25 (driven by LSI53C875) t 20 t 23 19 valid write data t 22s t 21 t 26
7-50 instruction set of the i/o processor 7.5 pci and external memory interface timing table 7.19 lists the LSI53C875 pci and external memory interface timing data. table 7.19 LSI53C875 pci and external memory interface timing symbol parameter min max unit t 1 shared signal input setup time 7 ns t 2 shared signal input hold time 0 ns t 3 clk to shared signal output valid 11 ns t 4 side signal input setup time 10 ns t 5 side signal input hold time 0 ns t 6 clk to side signal output valid 12 ns t 7 clk high to fetch/ low 20 ns t 8 clk high to fetch/ high 20 ns t 9 clk high to master/ low 20 ns t 10 clk high to master/ high 20 ns t 11 address setup to mas/ high 25 ns t 12 address hold from mas/ high 15 ns t 13 mas/ pulse width 25 ns t 14f mce/ low to data clocked in (fast memory) 160 ns t 14s mce/ low to data clocked in (slow memory) 220 ns t 15f address valid to data clocked in (fast memory) 205 ns t 15s address valid to data clocked in (slow memory) 265 ns t 16f moe/ low to data clocked in (fast memory) 100 ns t 16s moe/ low to data clocked in (slow memory) 160 ns t 17 data hold from address, moe/, mce/ change 0 ns t 18 next address out from moe/, mce/ high 50 ns t 19 data setup to clk high 5 ns t 20 data setup to mwe/ low 30 ns t 21 data hold from mwe/ high 20 ns t 25 mce/ low to mwe/ low 25 ns t 26 mwe/ high to mce/ high 25 ns
scsi timing diagrams 7-51 7.6 scsi timing diagrams table 7.20 through table 7.29 and figure 7.31 through figure 7.35 describe the LSI53C875 scsi timing. figure 7.31 initiator asynchronous send table 7.20 initiator asynchronous send symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 ns t 2 sack/ deasserted from sreq/ deasserted 5 ns t 3 data setup to sack/ asserted 55 ns t 4 data hold from sreq/ deasserted 20 ns sreq/ sack/ sd[15:0]/ sdp[1:0]/ t 1 t 2 t 3 t 4 n + 1 n valid n valid n + 1 n + 1
7-52 instruction set of the i/o processor figure 7.32 initiator asynchronous receive figure 7.33 target asynchronous send table 7.21 initiator asynchronous receive symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 ns t 2 sack/ deasserted from sreq/ deasserted 5 ns t 3 data setup to sreq/ asserted 0 ns t 4 data hold from sack/ asserted 0 ns table 7.22 target asynchronous send symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 ns t 2 sreq/ asserted from sack/ deasserted 5 ns t 3 data setup to sreq/ asserted 55 ns t 4 data hold from sack/ asserted 20 ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 1 t 2 n + 1 valid n + 1 valid n n t 3 t 4 n n + 1 valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
scsi timing diagrams 7-53 figure 7.34 target asynchronous receive figure 7.35 initiator and target synchronous transfer table 7.23 target asynchronous receive symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 ns t 2 sreq/ asserted from sack/ deasserted 5 ns t 3 data setup to sack/ asserted 0 ns t 4 data hold from sreq/ deasserted 0 ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ n n + 1 t 2 t 1 t 3 t 4 valid n valid n + 1 n + 1 n sreq/ or sack/ send data sd[15:0]/, sdp[1:0]/ receive data sd[15:0]/, sdp[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 n n + 1 valid n valid n + 1 valid n valid n + 1
7-54 instruction set of the i/o processor table 7.24 scsi-1 transfers (se, 5.0 mbytes/s) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 90 ns t 2 send sreq/ or sack/ deassertion pulse width 90 ns t 1 receive sreq/ or sack/ assertion pulse width 90 ns t 2 receive sreq/ or sack/ deassertion pulse width 90 ns t 3 send data setup to sreq/ or sack/ asserted 55 ns t 4 send data hold from sreq/ or sack/ asserted 100 ns t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 45 ns table 7.25 scsi-1 transfers (differential, 4.17 mbytes/s) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 96 ns t 2 send sreq/ or sack/ deassertion pulse width 96 ns t 1 receive sreq/ or sack/ assertion pulse width 84 ns t 2 receive sreq/ or sack/ deassertion pulse width 84 ns t 3 send data setup to sreq/ or sack/ asserted 65 ns t 4 send data hold from sreq/ or sack/ asserted 110 ns t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 45 ns
scsi timing diagrams 7-55 table 7.26 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 ns t 2 send sreq/ or sack/ deassertion pulse width 35 ns t 1 receive sreq/ or sack/ assertion pulse width 20 ns t 2 receive sreq/ or sack/ deassertion pulse width 20 ns t 3 send data setup to sreq/ or sack/ asserted 33 ns t 4 send data hold from sreq/ or sack/ asserted 40 ns t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 10 ns table 7.27 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 50 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 ns t 2 send sreq/ or sack/ deassertion pulse width 35 ns t 1 receive sreq/ or sack/ assertion pulse width 20 ns t 2 receive sreq/ or sack/ deassertion pulse width 20 ns t 3 send data setup to sreq/ or sack/ asserted 33 ns t 4 send data hold from sreq/ or sack/ asserted 40 1 1. analysis of system con?uration is recommended due to reduced driver skew margin in differential systems. notes: transfer period bits (bits [7:5] in the scsi transfer (sxfer) register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) ) is set. for fast scsi, set the tolerant enable bit (bit 7 in scsi test three (stest3) ). ?s t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 10 ns
7-56 instruction set of the i/o processor table 7.28 ultra scsi se transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 16 ns t 2 send sreq/ or sack/ deassertion pulse width 16 ns t 1 receive sreq/ or sack/ assertion pulse width 10 ns t 2 receive sreq/ or sack/ deassertion pulse width 10 ns t 3 send data setup to sreq/ or sack/ asserted 12 ns t 4 send data hold from sreq/ or sack/ asserted 17 ns t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 6 ns notes: transfer period bits (bits [7:5] in the scsi transfer (sxfer) register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) ) is set. for fast scsi, set the tolerant enable bit (bit 7 in scsi test three (stest3) ). during ultra scsi transfers, the value of the extend req/ ack filtering bit ( scsi test two (stest2) , bit 1) has no effect.
scsi timing diagrams 7-57 table 7.29 ultra scsi differential transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 16 ns t 2 send sreq/ or sack/ deassertion pulse width 16 ns t 1 receive sreq/ or sack/ assertion pulse width 10 ns t 2 receive sreq/ or sack/ deassertion pulse width 10 ns t 3 send data setup to sreq/ or sack/ asserted 16 ns t 4 send data hold from sreq/ or sack/ asserted 21 ns t 5 receive data setup to sreq/ or sack/ asserted 0 ns t 6 receive data hold from sreq/ or sack/ asserted 6 ns notes: transfer period bits (bits [7:5] in the scsi transfer (sxfer) register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) ) is set. for fast scsi, set the tolerant enable bit (bit 7 in scsi test three (stest3) ). during ultra scsi transfers, the value of the extend req/ ack filtering bit ( scsi test two (stest2) , bit 1) has no effect.
7-58 instruction set of the i/o processor 7.7 package drawings figure 7.36 is the 169-pin pbga mechanical drawing and figure 7.37 is the 160-pin pqfp mechanical drawing for the LSI53C875. figure 7.36 169-pin pbga (gv) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code gv.
package drawings 7-59 figure 7.37 160-pin pqfp (p3) mechanical drawing (sheet 1 of 2) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p3.
7-60 instruction set of the i/o processor figure 7.37 160-pin pqfp (p3) mechanical drawing (sheet 2 of 2) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p3.
LSI53C875/875e pci to ultra scsi i/o processor a-1 appendix a register summary table a.1 lists the LSI53C875 con?uration registers by register name. table a.1 con?uration registers register name address read/write page base address one (memory) 0x14 read/write 3-19 base address zero (i/o) 0x10 read/write 3-19 bridge support extensions (pmcsr_bse) 0x46 read only 3-27 cache line size 0x0c read/write 3-18 capabilities pointer 0x34 read only 3-22 capability id 0x40 read only 3-25 class code 0x09 read only 3-17 command 0x04 read/write 3-13 data 0x47 read only 3-28 device id 0x02 read only 3-13 expansion rom base address 0x30 read/write 3-21 header type 0x0e read only 3-19 interrupt line 0x3c read/write 3-23 interrupt pin 0x3d read only 3-23 latency timer 0x0d read/write 3-18 max_lat 0x3f read only 3-24 min_gnt 0x3e read only 3-24 next item pointer 0x41 read only 3-25
a-2 register summary table a.2 lists the LSI53C875 operating registers by register name. power management capabilities 0x42 read only 3-25 power management control/status 0x44 read/write 3-26 ram base address two (memory) scripts ram 0x18 read/write 3-20 revision id 0x08 read only 3-17 status 0x06 read/write 3-15 subsystem id (ssid) 0x2e read only 3-21 subsystem vendor id (ssvid) 0x2c read only 3-20 vendor id 0x00 read only 3-13 table a.1 con?uration registers (cont.) register name address read/write page table a.2 LSI53C875 register map register name address (memory or i/o) (con?. memory or i/o) read/write page adder sum output (adder) 0x3c?x3f (0xbc?xbf) read only 5-53 chip test five (ctest5) 0x22 (0xa2) read/write 5-42 chip test four (ctest4) 0x21 (0xa1) read/write 5-40 chip test one (ctest1) 0x19 (0x99) read only 5-35 chip test six (ctest6) 0x23 (0xa3) read/write 5-43 chip test three (ctest3) 0x1b (0x9b) read/write 5-37 chip test two (ctest2) 0x1a (0x9a) read/write 5-35 chip test zero (ctest0) 0x18 (0x98) read/write 5-34 data structure address (dsa) 0x10?x13 (0x90?x93) read/write 5-31 dma byte counter (dbc) 0x24?x26 (0xa4?xa6) read/write 5-44 dma command (dcmd) 0x27 (0xa7) read/write 5-45 dma control (dcntl) 0x3b (0xbb) read/write 5-51 dma fifo (dfifo) 0x20 (0xa0) read/write 5-39
register summary a-3 dma interrupt enable (dien) 0x39 (0xb9) read/write 5-50 dma mode (dmode) 0x38 (0xb8) read/write 5-47 dma next address (dnad) 0x28?x2b (0xa8?xab) read/write 5-45 dma scripts pointer (dsp) 0x2c?x2f (0xac?xaf) read/write 5-46 dma scripts pointer save (dsps) 0x30?x33 (0xb0?xb3) read/write 5-46 dma status (dstat) 0x0c (0x8c) read only 5-23 general purpose (gpreg) 0x07 (0x87) read/write 5-19 general purpose pin control (gpcntl) 0x47 (0xc7) read/write 5-63 interrupt status (istat) 0x14 (0x94) read/write 5-31 memory access control (macntl) 0x46 (0xc6) read/write 5-62 response id one (respid1) 0x4b (0xcb) read/write 5-70 response id zero (respid0) 0x4a (0xca) read/write 5-69 scratch byte register (sbr) 0x3a (0xba) read/write 5-51 scratch register a (scratcha) 0x34?x37 (0xb4?xb7) read/write 5-47 scratch register b (scratchb) 0x5c?x5f (0xdc?xdf) read/write 5-79 scratch registers c? (scratchc?cratchj) 0x60?x7f (0xe0?xff) read/write 5-79 scsi bus control lines (sbcl) 0x0b (0x8b) read only 5-22 scsi bus data lines (sbdl) 0x58?x59 (0xd8?xd9) read only 5-78 scsi chip id (scid) 0x04 (0x84) read/write 5-14 scsi control one (scntl1) 0x01 (0x81) read/write 5-6 scsi control three (scntl3) 0x03 (0x83) read/write 5-12 scsi control two (scntl2) 0x02 (0x82) read/write 5-9 scsi control zero (scntl0) 0x00 (0x80) read/write 5-3 table a.2 LSI53C875 register map (cont.) register name address (memory or i/o) (con?. memory or i/o) read/write page
a-4 register summary scsi destination id (sdid) 0x06 (0x86) read/write 5-18 scsi first byte received (sfbr) 0x08 (0x88) read/write 5-20 scsi input data latch (sidl) 0x50?x51 (0xd0?xd1) read only 5-77 scsi interrupt enable one (sien1) 0x41 (0xc1) read/write 5-55 scsi interrupt enable zero (sien0) 0x40 (0xc0) read/write 5-53 scsi interrupt status one (sist1) 0x43 (0xc3) read only 5-59 scsi interrupt status zero (sist0) 0x42 (0xc2) read only 5-56 scsi longitudinal parity (slpar) 0x44 (0xc4) read/write 5-60 scsi output control latch (socl) 0x09 (0x89) read/write 5-21 scsi output data latch (sodl) 0x54?x55 (0xd4?xd5) read/write 5-78 scsi selector id (ssid) 0x0a (0x09) read only 5-22 scsi status one (sstat1) 0x0e (0x8e) read only 5-27 scsi status two (sstat2) 0x0f (0x8f) read only 5-29 scsi status zero (sstat0) 0x0d (0x8d) read only 5-26 scsi test one (stest1) 0x4d (0xcd) read/write 5-72 scsi test three (stest3) 0x4f (0xcf) read/write 5-75 scsi test two (stest2) 0x4e (0xce) read/write 5-73 scsi test zero (stest0) 0x4c (0xcc) read only 5-70 scsi timer one (stime1) 0x49 (0xc9) read/write 5-66 scsi timer zero (stime0) 0x48 (0xc8) read/write 5-64 scsi transfer (sxfer) 0x05 (0x85) read/write 5-15 scsi wide residue (swide) 0x45 (0xc5) read/write 5-61 temporary (temp) 0x1c?x1f (0x9c?x9f) read/write 5-38 table a.2 LSI53C875 register map (cont.) register name address (memory or i/o) (con?. memory or i/o) read/write page
LSI53C875/875e pci to ultra scsi i/o processor b-1 appendix b external memory interface diagram examples figure b.1 64 kbyte interface with 200 ns memory LSI53C875 27c128 moe/ oe mce/ ce d0 8 mad[7:0] bus d7 q0 8 a[7:0] q7 6 a[13:8] 6 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 16 kbytes of slow memory (200 ns device @ 33 mhz). hct374 d[7:0] mad3 4.7 k mad2 4.7 k mad1 4.7 k mad0 4.7 k ck 0e d0 d5 q0 q5 hct374 ck 0e
b-2 external memory interface diagram examples figure b.2 64 kbyte interface with 150 ns memory LSI53C875 27c512-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 64 kbytes of fast memory (150 ns device @ 33 mhz). gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f512-15/ socket d[7:0] mad3 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e
external memory interface diagram examples b-3 figure b.3 256 kbyte interface with 150 ns memory LSI53C875 27c020-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 mas0/ mas1/ 8 note: mad bus sense logic enabled for 256 kbytes of fast memory (150 ns device @ 33 mhz). the hct374s may be replaced with hct377s. gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f020-15/ socket d[7:0] 2 2 a[17:16] v ss mad2 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d1 q0 q1 hct377 ck 0e mad[1:0] bus
b-4 external memory interface diagram examples figure b.4 512 kbyte interface with 150 ns memory LSI53C875 moe/ 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 512 kbytes of slow memory (150 ns devices, additional time required for hct139 @ 33 mhz). the hct374s may be replaced with hct377s. gpio4 mwe/ v pp control + 12 v v pp optional - for flash memory only, not required for eeproms. d[7:0] mad0 4.7 k 3 mad2 4.7 k oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 a b gb y0 y1 y2 y3 mce/ hct139 ce ce ce ce 27c010-15/28f010-15 sockets d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d2 q0 q2 hct377 ck 0e mad[2:0] bus a16 d7 d7 d7 d7 a17 a18
LSI53C875/875e pci to ultra scsi i/o processor ix-1 index numerics 3.3/5 volt pci interface 2-9 3-state 4-6 a abort operation bit 5-31 aborted bit 5-24 , 5-50 active negation see tolerant technology active termination 2-23 adder register 5-53 adder sum output register 5-53 always wide scsi bit 5-74 arbitration arbitration in progress bit 5-27 arbitration mode bits 5-3 immediate arbitration bit 5-8 in progress bit 5-27 lost arbitration bit 5-27 mode bits 5-3 priority encoder test bit 5-71 won arbitration bit 5-27 assert even scsi parity bit 5-7 assert satn/ on parity error bit 5-5 assert scsi ack/ signal bit 5-21 assert scsi atn/ signal bit 5-21 assert scsi bsy/ signal bit 5-21 assert scsi c_d/ signal bit 5-21 assert scsi data bus bit 5-6 assert scsi i_o signal bits 5-21 assert scsi msg/ signal bit 5-21 assert scsi req/ signal bit 5-21 assert scsi rst/ signal bit 5-7 assert scsi sel/ signal bit 5-21 b bidirectional 4-6 big and little endian support 2-10 block move instructions 6-5 burst disable bit 5-40 burst length bits 5-43 , 5-47 burst opcode fetch enable bit 5-49 bus fault bit 5-24 , 5-50 byte empty in dma fifo (fmt) 5-34 byte empty in dma fifo bit 5-35 byte full in dma fifo bit 5-35 byte offset counter bits 5-39 , 5-43 c cache line size enable bit 5-51 cache mode, see pci cache mode 3-4 chained block moves 2-34 to 2-38 sodl register 2-36 swide register 2-36 wide scsi receive bit 2-36 wide scsi send bit 2-35 chained mode bit 5-9 chip revision level bits 5-37 chip test five register 5-42 chip test four register 5-40 chip test one register 5-35 chip test six register 5-43 chip test two register 5-35 chip test zero register 5-34 chip type bits 5-62 clear dma fifo bit 5-37 clear scsi fifo bit 5-76 clock address incrementor bit 5-42 clock byte counter bit 5-42 clock conversion factor bits 5-13 configuration registers. see pci configuration registers configured as i/o bit 5-36 configured as memory bit 5-36 connected bit 5-7 , 5-33 ctest0 register 5-34 ctest1 register 5-35 ctest2 register 5-35 ctest4 register 5-40 ctest5 register 5-42 ctest6 register 5-43 d data acknowledge status bit 5-37 data path 2-16 data request status bit 5-37 data structure address register 5-31 data transfer direction bit 5-35 datard bit 5-62 datawr bit 5-62 dbc register 5-44 dblen bit 3 5-72 dblsel bit 2 5-72 dcmd register 5-45 dcntl register 5-51 destination i/o memory enable bit 5-48 dfifo register 5-39 dien register 5-50
ix-2 index dif bit 5-73 differential mode diffsens 4-19 direction control pins 4-16 operation 2-20 scsi differential mode bit 5-73 diffsens scsi signal 7-3 disable halt on parity error or atn 5-7 disable single initiator response bit 5-76 dma byte counter register 5-44 dma command register 5-45 dma control register 5-51 dma core 2-2 dma direction bit 5-42 dma fifo bits 5-43 dma fifo empty bit 5-23 dma fifo register 5-39 dma fifo size bit 5-42 dma interrupt enable register 5-50 dma interrupt pending bit 5-34 dma mode register 5-47 dma next address register 5-45 dma scripts pointer register 5-46 dma scripts pointer save register 5-46 dma status register 5-23 dmode register 5-47 dnad register 5-45 dsa register 5-31 dsp register 5-46 dsps register 5-46 dstat register 5-23 e enable parity checking bit 5-5 enable read line bit 5-49 enable read multiple bit 5-49 enable response to reselection bit 5-14 enable response to selection bit 5-14 enable wide scsi bit 5-12 encoded chip scsi id 5-14 encoded destination scsi id bit 5-22 encoded destination scsi id bits 5-18 extend sreq/sack filtering bit 5-74 external memory interface 2-6 , 2-7 configuration 2-7 flash rom updates 2-6 gpio4 bit 5-19 multiple byte accesses 7-13 slow memory 2-8 system requirements 2-6 extra clock cycle of data setup bit 5-6 f fetch enable 5-63 fetch pin mode bit 5-38 fifo byte control bits 5-41 fifo flags bits 5-27 , 5-30 flush dma fifo bit 5-37 fmt 5-34 function complete bit 5-54 , 5-57 g general purpose pin control register 5-63 general purpose register 5-19 general purpose timer expired bit 5-56 , 5-59 general purpose timer period bits 5-68 general purpose timer scale factor bit 5-66 gpcntl register 5-63 gpio enable bit 5-63 gpio[4:0] bits 5-19 gpreg register 5-19 h halt scsi clock bit 5-76 handshake-to-handshake timer bus activity enable bit 5-66 handshake-to-handshake timer expired bit 5-56 , 5-59 handshake-to-handshake timer period bit 5-64 high impedance mode bit 5-40 i i/o instructions 6-12 illegal instruction detected bit 5-24 immediate arbitration bit 5-8 input 4-6 instruction prefetching 2-5 prefetch enable bit 5-51 prefetch flush bit 5-51 prefetch unit flushing 2-5 instructions block move 6-5 i/o 6-12 load and store 6-37 memory move 6-33 read/write 6-21 transfer control 6-26 internal ram, see also scripts ram 2-3 interrupt status register 5-31 interrupt-on-the-fly bit 5-33 interrupts fatal vs. nonfatal interrupts 2-30 halting 2-33 irq disable bit 2-30 masking 2-31 sample interrupt service routine 2-33 stacked interrupts 2-32 irq disable bit 5-52 irq mode bit 5-52 istat register 5-31 j jtag support 2-10 l last disconnect bit 5-30 latched scsi parity bit 5-28 latched scsi parity for sd[15:8] bit 5-30 load and store instructions 6-37 no flush option 6-38 prefetch unit and store instructions 2-6 , 6-38 lost arbitration bit 5-27 lsi53c700 family compatibility bit 5-53
index ix-3 m macntl register 5-62 mad bus programming 4-22 mad[0] 4-24 mad[3:1] 4-24 mad[4] 4-23 mad[5] 4-23 mad[6] 4-23 mad[7] 4-22 manual start mode bit 5-49 master control for set or reset pulses bit 5-42 master data parity error bit 5-24 , 5-50 master enable bit 5-63 master parity error enable bit 5-41 max scsi synchronous offset bits 5-17 memory access control register 5-62 memory move instructions 6-33 and scripts instruction prefetching 2-5 no flush option 2-5 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 write and invalidate mode bit 3-14 mg[7:0] 3-24 min_gnt (mg[7:0]) 3-24 n no flush memory move instruction 6-34 o opcode fetch bursting 2-6 operating registers adder sum output 5-53 chip test five 5-42 chip test four 5-40 chip test one 5-35 chip test six 5-43 chip test three 5-37 chip test two 5-35 chip test zero 5-34 data structure address 5-31 dma byte counter 5-44 dma command 5-45 dma control 5-51 dma fifo 5-39 dma interrupt enable 5-50 dma mode 5-47 dma next address 5-45 dma scripts pointer 5-46 dma scripts pointer save 5-46 dma status 5-23 general information 5-1 general purpose 5-19 general purpose pin control 5-63 interrupt status 5-31 memory access control 5-62 response id one 5-70 response id zero 5-69 scratch byte 5-51 scratch register a 5-47 scratch register b 5-79 scsi bus control lines 5-22 scsi bus data lines 5-78 scsi chip id 5-14 scsi control one register 5-6 scsi control register two 5-9 scsi control three 5-12 scsi control zero 5-3 scsi destination id 5-18 scsi first byte received 5-20 scsi input data latch 5-77 scsi interrupt enable one 5-55 scsi interrupt enable zero 5-53 scsi interrupt status one 5-59 scsi interrupt status zero 5-56 scsi longitudinal parity 5-60 scsi output control latch 5-21 scsi output data latch 5-78 scsi selector id 5-22 scsi status one 5-27 scsi status two 5-29 scsi status zero 5-26 scsi test one 5-72 scsi test three 5-75 scsi test two 5-73 scsi test zero 5-70 scsi timer one 5-66 scsi timer zero 5-64 scsi transfer 5-15 scsi wide residue 5-61 temporary stack 5-38 p package and feature options 1-4 parity 2-12 parity error bit 5-58 pci cache mode 3-4 cache line size enable bit 5-51 cache line size register 3-18 enable read multiple bit 5-49 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 write and invalidate mode bit 3-14 write and invalidate enable bit 5-38 pci commands 3-2 pci configuration registers 3-11 to 3-24 base address one (memory) 3-19 base address zero (i/o) 3-19 cache line size 3-18 class code 3-17 command 3-13 data 3-28 device id 3-13 expansion rom base address 3-21 header type 3-19 interrupt line 3-23 interrupt pin 3-23 latency timer 3-18 max_lat 3-24 min_gnt 3-24 next item pointer 3-25 power management control/status 3-26 revision id 3-17 status 3-15 subsystem data 3-20 subsystem id (ssid) 3-21
ix-4 index subsystem vendor id (ssvid) 3-20 vendor id 3-13 pci configuration space 3-1 pci i/o space 3-2 pci memory space 3-2 pci timings 7-50 phase mismatch bit 5-57 pointer scripts bit 5-62 power management power state d0 2-38 power state d3 2-39 prefetch enable bit 5-51 prefetch flush bit 5-51 r ram, see also scripts ram 2-3 read/write instructions 6-21 register addresses operating registers 0x00 5-3 0x01 5-6 0x02 5-9 0x03 5-12 0x04 5-14 0x05 5-15 0x06 5-18 0x07 5-19 0x08 5-20 0x09 5-21 0x0a 5-22 0x0b 5-22 0x0c 5-23 0x0d 5-26 0x0e 5-27 0x0f 5-29 0x10?x13 5-31 0x14 5-31 0x18 5-34 0x19 5-35 0x1a 5-35 0x1b 5-37 0x1c?x1f 5-38 0x20 5-39 0x21 5-40 0x22 5-42 0x23 5-43 0x24?x26 5-44 0x27 5-45 0x28?x2b 5-45 0x2c?x2f 5-46 0x30?x33 5-46 0x34?x37 5-47 0x38 5-47 0x39 5-50 0x3a 5-51 0x3b 5-51 0x3c?x3f 5-53 0x40 5-53 0x41 5-55 0x42 5-56 0x43 5-59 0x44 5-60 0x45 5-61 0x46 5-62 0x47 5-63 0x48 5-64 0x49 5-66 0x4a 5-69 0x4b 5-70 0x4c 5-70 0x4d 5-72 0x4e 5-73 0x4f 5-75 0x50?x51 5-77 0x54?x55 5-78 0x58?x59 5-78 0x5c?x5f 5-79 0x60?x70 5-79 pci configuration registers 0x00 3-13 0x02 3-13 0x04 3-13 0x06 3-15 0x08 3-17 0x0c 3-18 0x0d 3-18 0x0e 3-19 0x10 3-19 0x14 3-19 0x18 3-20 0x2c 3-20 0x2e 3-21 0x30 3-21 0x34 3-22 0x3c 3-23 0x3d 3-23 0x3e 3-24 0x3f 3-24 0x40 3-25 0x41 3-25 0x42 3-25 0x44 3-26 0x46 3-27 0x47 3-28 subsystem data 3-20 register bits abort operation 5-31 aborted 5-24 , 5-50 always wide scsi 5-74 arbitration priority encoder test 5-71 arbitration in progress 5-27 arbitration mode 5-3 assert even scsi parity (force bad parity)) 5-7 assert satn/ on parity error 5-5 assert scsi ack/ signal 5-21 assert scsi atn/ signal 5-21 assert scsi bsy/ signal 5-21 assert scsi c_d/ signal 5-21 assert scsi data bus 5-6 assert scsi i_o/ signal 5-21 assert scsi msg/ signal 5-21 assert scsi req/ signal 5-21 assert scsi rst/ signal 5-7 assert scsi sel/ signal 5-21 burst disable 5-40 burst length 5-43 , 5-47 burst opcode fetch enable 5-49 bus fault 5-24 , 5-50 byte empty in dma fifo 5-35 byte full in dma fifo 5-35
index ix-5 byte offset counter 5-39 , 5-43 cache line size enable 5-51 chained mode 5-9 chip revision level 5-37 chip type 5-62 clear dma fifo 5-37 clear scsi fifo 5-76 clock address incrementor 5-42 clock byte counter 5-42 clock conversion factor 5-13 configured as i/o 5-36 configured as memory 5-36 connected 5-7 , 5-33 data acknowledge status 5-37 data request status 5-37 data transfer direction 5-35 datard 5-62 datawr 5-62 destination i/o memory enable 5-48 disable halt on parity error or atn 5-7 disable single initiator response 5-76 dma direction 5-42 dma fifo 5-43 dma fifo empty 5-23 dma fifo size 5-42 dma interrupt pending 5-34 enable parity checking 5-5 enable read line 5-49 enable read multiple 5-49 enable response to reselection 5-14 enable response to selection 5-14 enable wide scsi 5-12 encoded chip scsi id, bits [3:0] 5-14 encoded destination scsi id 5-18 , 5-22 extend sreq/sack filtering 5-74 extra clock cycle of data setup 5-6 fetch enable 5-63 fetch pin mode 5-38 fifo byte control 5-41 fifo flags 5-27 , 5-30 flush dma fifo 5-37 function complete 5-54 , 5-57 general purpose timer expired 5-56 , 5-59 general purpose timer period 5-68 general purpose timer scale factor 5-66 gpio enable 5-63 gpio[4:0] 5-19 halt scsi clock 5-76 handshake-to-handshake timer bus activity enable 5-66 handshake-to-handshake timer expired 5-56 , 5-59 handshake-to-handshake timer period 5-64 high impedance mode 5-40 illegal instruction detected 5-24 , 5-50 immediate arbitration 5-8 interrupt-on-the-fly 5-33 irq disable 5-52 irq mode 5-52 last disconnect 5-30 latched scsi parity 5-28 latched scsi parity for sd[15:8] 5-30 lost arbitration 5-27 lsi53c700 family compatibility 5-53 manual start mode 5-49 master control for set or reset pulses 5-42 master data parity error 5-24 , 5-50 master enable 5-63 master parity error enable 5-41 max scsi synchronous offset 5-17 parity error 5-58 phase mismatch 5-57 pointer scripts 5-62 prefetch enable 5-51 prefetch flush 5-51 reselected 5-54 , 5-57 reset scsi offset 5-73 sack/ status 5-22 satn/ status 5-22 sbsy/ status 5-22 sc_d/ status 5-23 sclk 5-72 sclk doubler enable bit 5-72 sclk doubler select bit 5-72 scratcha/b operation 5-36 scripts 5-62 scripts interrupt instruction received 5-24 , 5-50 scsi c_d/ signal 5-28 scsi control enable 5-73 scsi data high impedance 5-40 scsi differential mode 5-73 scsi disconnect unexpected 5-9 scsi fifo test read 5-75 scsi fifo test write 5-77 scsi gross error 5-54 , 5-57 scsi high impedance mode 5-74 scsi i_o/ signal 5-28 scsi interrupt pending 5-33 scsi isolation mode 5-72 scsi loopback mode 5-74 scsi low level mode 5-74 scsi msg/ signal 5-28 scsi parity error 5-55 scsi phase mismatch - initiator mode 5-54 scsi reset condition 5-55 scsi rst/ received 5-58 scsi rst/ signal 5-27 scsi sdp0/ parity signal 5-27 scsi sdp1 signal 5-30 scsi selected as id 5-70 scsi synchronous offset maximum 5-71 scsi synchronous offset zero 5-71 scsi synchronous transfer period 5-15 scsi true end of process 5-36 scsi valid 5-22 select with satn/ on a start sequence 5-4 selected 5-54 , 5-57 selection or reselection time-out 5-56 , 5-59 selection response logic test 5-71 selection time-out 5-65 semaphore 5-32 shadow register test mode 5-40 si_o/ status 5-23 sidl least significant byte full 5-26 sidl most significant byte full 5-29 signal process 5-32 , 5-36 single step interrupt 5-24 , 5-50 single step mode 5-51 slpar high byte enable 5-10 slpar mode 5-10 smsg/ status 5-23 sodl least significant byte full 5-26 sodl most significant byte full 5-29 sodr least significant byte full 5-26
ix-6 index sodr most significant byte full 5-29 software reset 5-32 source i/o memory enable 5-48 sreq/ status 5-22 ssel/ status 5-22 start dma operation 5-52 start scsi transfer 5-8 start sequence 5-4 synchronous clock conversion factor 5-12 target mode 5-6 timer test mode 5-76 tolerant enable 5-75 ultra enable 5-12 unexpected disconnect 5-55 , 5-58 wide scsi receive 5-11 wide scsi send 5-10 won arbitration 5-27 write and invalidate enable 5-38 reselected bit 5-54 , 5-57 reset scsi offset bit 5-73 respid0 register 5-69 respid1 register 5-70 response id one register 5-70 response id zero register 5-69 revision level bits 5-37 s sack/ status bit 5-22 satn/ active 5-57 satn/ active bit 5-57 satn/ status bit 5-22 sbcl register 5-22 sbdl register 5-78 sbr register 5-51 sbsy status bit 5-22 sc_d/ status bit 5-23 scid register 5-14 sclk bit 5-72 scntl0 register 5-3 scntl1 register 5-6 scntl2 register 5-9 scntl3 register 5-12 scratch register 5-51 scratcha register 5-47 scratcha/b operation bit 5-36 scratchb register 5-79 scripts bit 5-62 scripts interrupt instruction received bit 5-24 scripts processor 2-2 instruction prefetching 2-5 internal ram for instruction storage 2-3 performance 2-2 scripts ram 2-3 scratcha/b operation bit 5-36 scsi core 2-1 differential mode 2-20 termination 2-23 timings 7-51 tolerant technology 1-5 scsi atn condition - target mode 5-54 scsi atn condition bit 5-54 scsi bus control lines register 5-22 scsi bus data lines register 5-78 scsi bus interface 2-19 to 2-25 scsi c_d/ signal bit 5-28 scsi chip id register 5-14 scsi control enable bit 5-73 scsi control one register 5-6 scsi control three register 5-12 scsi control two register 5-9 scsi control zero register 5-3 scsi core 2-1 scsi data high impedance bit 5-40 scsi destination id register 5-18 scsi differential mode bit 5-73 scsi disconnect unexpected bit 5-9 scsi fifo test read bit 5-75 scsi fifo test write bit 5-77 scsi first byte received register 5-20 scsi gross error bit 5-54 , 5-57 scsi high impedance mode bit 5-74 scsi i_o/ signal bit 5-28 scsi input data latch register 5-77 scsi instructions block move 6-5 i/o 6-12 load/store 6-37 memory move 6-33 read/write 6-21 transfer control 6-26 scsi interrupt enable one register 5-55 scsi interrupt enable zero register 5-53 scsi interrupt pending bit 5-33 scsi interrupt status one register 5-59 scsi interrupt status zero register 5-56 scsi isolation mode bits 5-72 scsi longitudinal parity register 5-60 scsi loopback mode bit 5-74 scsi low level mode bit 5-74 scsi msg/ signal bit 5-28 scsi output control latch register 5-21 scsi output data latch register 5-78 scsi parity error bit 5-55 scsi phase mismatch bit 5-54 scsi reset condition bit 5-55 scsi rst/ received bit 5-58 scsi rst/ signal bit 5-27 scsi scripts operation 6-1 sample instruction 6-3 scsi sdp0/ parity signal bit 5-27 scsi sdp1 signal bit 5-30 scsi selected as id bits 5-70 scsi selector id register 5-22 scsi status one register 5-27 scsi status two register 5-29 scsi status zero register 5-26 scsi synchronous offset maximum 5-71 scsi synchronous offset zero bit 5-71 scsi test one register 5-72 scsi test three register 5-75 scsi test two register 5-73 scsi test zero register 5-70 scsi timer one register 5-66 scsi timer zero register 5-64 scsi timing diagrams 7-51 scsi transfer register 5-15 scsi true end of process bit 5-36 scsi valid bit 5-22 scsi wide residue register 5-61 sdid register 5-18
index ix-7 select with satn/ on a start sequence bit 5-4 selected bit 5-54 , 5-57 selection or reselection time-out bit 5-56 , 5-59 selection response logic test bits 5-71 semaphore bit 5-32 sfbr register 5-20 shadow register test mode bit 5-40 si_o/ status bit 5-23 sidl least significant byte full bit 5-26 sidl most significant byte full bit 5-29 sidl register 5-77 sien0 register 5-53 sien1 register 5-55 sigp bit 5-32 , 5-36 single step interrupt bit 5-24 , 5-50 single step mode bit 5-51 single-ended operation 2-19 sist0 register 5-56 sist1 register 5-59 slpar high byte enable 5-10 slpar mode bit 5-10 slpar register 5-60 smsg/ status bit 5-23 socl least significant byte full bit 5-26 socl register 5-21 sodl most significant byte full bit 5-29 sodl register 5-78 sodr least significant byte full bit 5-26 sodr most significant byte full bit 5-29 software reset bit 5-32 source i/o memory enable bit 5-48 sreq/ status bit 5-22 ssel/ status bit 5-22 ssid register 5-22 sstat0 register 5-26 sstat1 register 5-27 sstat2 register 5-29 stacked interrupts 2-32 start dma operation bit 5-52 start scsi transfer 5-8 start sequence bits 5-4 stest0 register 5-70 stest1 register 5-72 stest2 register 5-73 stest3 register 5-75 stime0 register 5-64 stime1 register 5-66 storage device management system (sdms) 2-3 swide register 5-61 sxfer register 5-15 synchronous clock conversion factor bits 5-12 synchronous data transfer rates 2-26 synchronous transfer period bits 5-15 t target mode bit 5-6 temp register 5-38 temporary register 5-38 termination 2-23 timer test mode bit 5-76 timings pci 7-50 scsi 7-51 tolerant 7-7 tolerant enable bit 5-75 tolerant technology 1-5 benefits 1-5 extend sreq/sack filtering bit 5-74 tolerant enable bit 5-75 totem pole output 4-6 transfer control instructions 6-26 and scripts instruction prefetching 2-6 transfer rate 1-6 synchronous 2-26 u ultra ultra enable bit 5-12 ultra scsi benefits 1-4 designing an ultra scsi system 2-4 synchronous transfer period bits 5-15 unexpected disconnect bit 5-55 , 5-58 w watn/ bit 5-4 wide scsi always wide scsi bit 5-74 chained block moves 2-34 chained mode bit 5-9 enable wide scsi bit 5-12 swide register 5-61 wide scsi receive bit 5-11 wide scsi send bit 5-10 wide scsi receive bit 5-11 wide scsi send bit 5-10 won arbitration bit 5-27 write and invalidate enable bit 5-38
ix-8 index
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